* Recipe parse & build errors fixed
* Use A proper init.d script skeleton
* change RC update params

* Usefull if rebuilding

* Use ch8, with correct address offset from AXI MM PS

* Add a link to the correct mapt file
* Add a default configuration

* Disposed on a shared URL

* This parse a configuration file and then load the FPGA with the
  correct bitstream (centralnode or cellnode)

* Else it is not possible to  make the device tree blob when several
  variants are given. Getting a duplicate node error.

* Turns ou I fail to make a /dev/axiapp pop in the FS... For now let's
  keep it as /dev/uio0

* Patch the .mapt file to set BAR to 0
* Add timers to xml config
* fix the device name

* This rely on the ChimeraTK GenericServer-OPCUA CSA
* It adds to the target filesystem the map and config files

TODO
+Script to launch the server at startup

* This generate a UIO device for the APP area.
* UIO is accessible in /dev/axiapp

It's better to fix it in Techlab layer.

* As we don't use block design, this IP is not detected automatically.
* The IP is located at a fixed address on the bus.

* Actualize the application
* No more BD inside
* Has a Debug Bridge at 0xA1000000

Struggling with petalinux update: it is no longer possible to log as
root without the tweaks.

From user diag, it is possible to sudo.

The one included by techlab-bsp matches their FPGA BSP.
I'm using MSK BSP

* move recipes to a identical filepath

* Use their headless recipe
* overlay external_hdf, add one xsa (central node)
* Include PyTango in image