* This is used for debug via xilinx tool. Not used and delaying boot
  when ILA not implemented

* New registers for cellnode: comlbp, ccnpack latched sequence
* New registers for centralnode: multrate
* Increase size of centralnode matrix

* This is a way to allow write from tango device, otherwise the type
  seems badly handled

* First time without Device Tree Overlay

* rename it app.dmap

* Using the dt overlay file shipped when programming the FPGA
* Start the daemon mmcctrld afterward. This will do a nice shutdown when
  MMC signals stop.

* This allow adding the i2c to MMC

* Since LNM is used, generix device server only writes 0 in registers
  that are mapped

* Type, missing hier in path

* It is now possible to use symlink in devices.dmap, deviceaccess fixed
  We will use symlinks created by udev rules.
* All link decision is done by fofb-init

* default to one server: 'ntp'

* Append the recipe with the on the fly fix for mapt

* Probably best practice

* Add conversion to Amps on PSC command
* Add access to number of BPM in the correction

* Quick patch, better working on it elsewhere
* The 2D array is given line by line in the MAPT file
* This AWK rules replace that with a single global line

* Somehow this won't work when called by rc at startup

BRONES Romain authored 1 year ago and BRONES Romain committed 1 year ago

* Remove unsused configuration.
* Add a comment with static configuration for wired interface.

BRONES Romain authored 1 year ago and BRONES Romain committed 1 year ago

* The LNM now adds 1 to the register value

* The OPCUA Generic server now only use this
* The proper LNM is selected from app name

* Add a reload statement to only reprog the FPGA
* FPGA bitstream is now linked
* Conf is always read
* Change status

* Need that to enable the full chain.
* Setting is no ticker

* also switch configuration file to an .example to avoid overwrite

* Configure and Start DAQ with ChimeraTK accessors.
* MMAP and copy to file

TODO
* Switch buffer
* rolling file destination
* Both BPM and PSC

* Use the lock file to store status
* While server is starting, the status will be "starting"
* After proper start, apply a FPGA reset and local config

* First IRQ of Group0 used for UIO DDR device
* Second to a new device

* Still under test

* Log on Reset and configure FPGA are pushed to log file