* This is handled better by DESYRDL

*  Instead of deriving ID field width

* Correction on testcase
* Add data source files
* update the python script that creates the data files

* Fix delay on matmul valid signal
* Fix length of validity for correction output

* Matmul coefs are now on 24 bits (23 effectives)
* Round more after matmul to keep result on 32b

All x then all y coefs

* Tie version register
* Import lib
* Copy data input before simulation

* There are always a couple of bits more on the address bus.
* Use a constant for data serializer ram

* This avoid a nasty bug in GHDL (LLVM backend) which doesn't work well
  with files with same names. We have another file named that way with
  DESYRDL.

* Also change the package constant declaration, add a few. All
  mathematic will be done outside of the package.