- May 22, 2024
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BRONES Romain authored
* Allow ID up to 255 * This changes dimension of memories, registers
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- Oct 30, 2023
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BRONES Romain authored
* Same generic bloc for operations * Capture the stream of data and retains accumulator in memory * Mirror memory for CPU readout wip: initial commit wip: Now a more generic bloc wip: Add average tables to RDL wip: integrate ma for oe in toplevel wip: first corrections for simulation, alpha declared in package wip: fixes for simulation wip: fixes, secondary memory is smaller, no decimal part wip: true rounding before wrinting to secondary memory wip: Add average for PSC command wip: fix sign extension on average orbit read
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- Jun 23, 2023
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BRONES Romain authored
* The corrector contains 4 coefficients that are enought to make a lag-compensator or lead-compensator * Change the name of the block to erase "pi" * Update the simulation data !! Still error on simulation, to be fixed
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- Jun 02, 2023
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BRONES Romain authored
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- Jun 01, 2023
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BRONES Romain authored
* Matmul coefs are now on 24 bits (23 effectives) * Round more after matmul to keep result on 32b
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- May 02, 2023
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BRONES Romain authored
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- Apr 28, 2023
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BRONES Romain authored
* There are always a couple of bits more on the address bus. * Use a constant for data serializer ram
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BRONES Romain authored
* This avoid a nasty bug in GHDL (LLVM backend) which doesn't work well with files with same names. We have another file named that way with DESYRDL.
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BRONES Romain authored
* Also change the package constant declaration, add a few. All mathematic will be done outside of the package.
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- Apr 26, 2023
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BRONES Romain authored
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