fix(sim): Fix simulation

* Add constant for number of BPM
* Change the register addresses

sim/tb_corr_matrix.vhd

@@ -122,6 +122,7 @@ begin
     port map(
         clk            => tb_clk,
         rst_n          => tb_rst_n,
+        pps            => '0',
 
         -- AXI-MM interface
         s_axi_m2s      => tb_s_axi_m2s,

sim/tc_basic.vhd

@@ -6,6 +6,7 @@ architecture basic of TestCtrl is
     ------------------------
     -- SIGNAL DECLARATION --
     ------------------------
+    constant C_NUMBPM : positive := 122;
     signal ConfigDone : integer_barrier := 1 ;
     signal TestDone : integer_barrier := 1 ;
 
@@ -90,15 +91,26 @@ begin
         log("+-- Global Config", INFO);
 
         -- Correction coefficients
-        Write(ManagerRec, f_addr(16#10#), f_sdata(218));
-        Write(ManagerRec, f_addr(16#14#), f_sdata(-186));
-        Write(ManagerRec, f_addr(16#18#), f_sdata(325));
-        Write(ManagerRec, f_addr(16#1C#), f_sdata(-3225));
-
-        Write(ManagerRec, f_addr(16#20#), f_sdata(128));
-        Write(ManagerRec, f_addr(16#24#), f_sdata(0));
-        Write(ManagerRec, f_addr(16#28#), f_sdata(8192));
+        Write(ManagerRec, f_addr(16#18#), f_sdata(218));
+        Write(ManagerRec, f_addr(16#1C#), f_sdata(-186));
+        Write(ManagerRec, f_addr(16#20#), f_sdata(325));
+        Write(ManagerRec, f_addr(16#24#), f_sdata(-3225));
+        Write(ManagerRec, f_addr(16#38#), f_sdata(218));
+        Write(ManagerRec, f_addr(16#3C#), f_sdata(-186));
+        Write(ManagerRec, f_addr(16#40#), f_sdata(325));
+        Write(ManagerRec, f_addr(16#44#), f_sdata(-3225));
+
+        Write(ManagerRec, f_addr(16#28#), f_sdata(128));
         Write(ManagerRec, f_addr(16#2C#), f_sdata(0));
+        Write(ManagerRec, f_addr(16#30#), f_sdata(8192));
+        Write(ManagerRec, f_addr(16#34#), f_sdata(0));
+        Write(ManagerRec, f_addr(16#48#), f_sdata(128));
+        Write(ManagerRec, f_addr(16#4C#), f_sdata(0));
+        Write(ManagerRec, f_addr(16#50#), f_sdata(8192));
+        Write(ManagerRec, f_addr(16#54#), f_sdata(0));
+
+        -- Num BPM
+        Write(ManagerRec, f_addr(16#58#), f_data(C_NUMBPM));
 
         -- Rst corr and threshold
         Write(ManagerRec, f_addr(8), f_sdata(10));
@@ -176,7 +188,7 @@ begin
         while nturn <  20 loop
             readline(read_file, line_v);
 
-            for I in 0 to 121 loop
+            for I in 0 to C_NUMBPM-1 loop
                 read(line_v, intx_v);
                 read(line_v, inty_v);