Modify corrector filter

* add round of 8 bits on mult A
* Add a pipeline stage

hdl/corr_ll.vhd

@@ -40,7 +40,7 @@ end entity corr_ll;
 
 architecture rtl of corr_ll is
 
-    constant C_DELAY    : natural := 4;
+    constant C_DELAY    : natural := 5;
     type arr_slv is array (natural range <>) of std_logic_vector;
     signal delay_valid  : std_logic_vector(C_DELAY-1 downto 0);
     signal delay_seq    : arr_slv(0 to C_DELAY-1)(C_W_BPMSEQ-1 downto 0);
@@ -129,6 +129,9 @@ begin
                 sum_abd         <= (others => '0');
                 reg_din         <= (others => '0');
                 reg_dout        <= (others => '0');
+                rz_mult_a       <= (others => '0');
+                rz_mult_b       <= (others => '0');
+                rz_mult_d       <= (others => '0');
             elsif rising_edge(clk) then
 
                 if reset_corr = '1' then
@@ -152,19 +155,29 @@ begin
                 if reset_corr = '1' then
                     reg_dout    <= (others => '0');
                 else
-                    if delay_valid(2) = '1' and enable_corr = '1' then
+                    if delay_valid(delay_valid'left-1) = '1' and enable_corr = '1' then
                         reg_dout        <= f_resize_sat(rnd_abicd, C_W_COR);
                     end if;
                 end if;
 
+                -- Round and resize
+                if mult_a(C_N_A_RND-1) = '0' then
+                    rz_mult_a   <= f_resize_sat(
+                                        f_resize_lsb(mult_a, mult_a'length-C_N_A_RND),
+                                   C_W_COR_SUMSAT);
+                else
+                    rz_mult_a   <= f_resize_sat(
+                                       f_sum_sat(f_resize_lsb(mult_a, mult_a'length-C_N_A_RND), to_signed(1, mult_a'length)),
+                                   C_W_COR_SUMSAT);
+                end if;
+
+                -- resize
+                rz_mult_b   <= f_resize_sat(mult_b, C_W_COR_SUMSAT);
+                rz_mult_d   <= f_resize_sat(mult_d, C_W_COR_SUMSAT);
+
             end if;
         end process;
 
-        -- resize
-        rz_mult_a   <= f_resize_sat(mult_a, C_W_COR_SUMSAT);
-        rz_mult_b   <= f_resize_sat(mult_b, C_W_COR_SUMSAT);
-        rz_mult_d   <= f_resize_sat(mult_d, C_W_COR_SUMSAT);
-
         -- round then sat
         rnd_abicd       <= f_resize_lsb(mult_ic, rnd_abicd'length) when mult_ic(C_N_COR_RND-1) = '0' else
                            f_sum_sat(f_resize_lsb(mult_ic, rnd_abicd'length), to_signed(1, rnd_abicd'length));