data_serializer.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library desy;
use desy.ram_tdp;

library desyrdl;
use desyrdl.pkg_corr_matrixpi.t_mem_PSCIDTABLE_out;
use desyrdl.pkg_corr_matrixpi.t_mem_PSCIDTABLE_in;

use work.pkg_corr_matrixpi.all;

entity data_serializer is
    port(
        clk             : in std_logic;
        rst_n           : in std_logic;

        -- PSCID memory
        pscid_table_i   : in t_mem_PSCIDTABLE_out;
        pscid_table_o   : out t_mem_PSCIDTABLE_in;

        -- Status
        overrun         : out std_logic;

        -- Corr parallel input
        corrout_valid   : in std_logic;
        corrout_seq     : in std_logic_vector(C_W_BPMSEQ-1 downto 0);
        corrout         : in signed_array(0 to C_N_MM_PSC-1)(C_W_COR-1 downto 0);

        -- AXIS serial output
        m_axis_tdata    : out std_logic_vector(C_W_COR+C_W_PSCID-1 downto 0);
        m_axis_tuser    : out std_logic_vector(C_W_BPMSEQ-1 downto 0);
        m_axis_tvalid   : out std_logic;
        m_axis_tready   : in std_logic
    );
end entity data_serializer;

architecture rtl of data_serializer is


    ------------------------
    -- SIGNAL DECLARATION --
    ------------------------
    signal cnt              : unsigned(C_W_SER_CNT-1 downto 0);
    signal run_serial       : std_logic;

    signal pscid            : std_logic_vector(C_W_PSCID-1 downto 0);

    signal r_corr           : signed_array(0 to C_N_MM_PSC-1)(C_W_COR-1 downto 0);
    signal r_seq            : std_logic_vector(C_W_BPMSEQ-1 downto 0);

begin

    ------------------------
    -- SERIALIZER COUNTER --
    ------------------------
    p_cnt:process(clk, rst_n)
    begin
        if rst_n = '0' then
            cnt         <= (others => '0');
            run_serial  <= '0';
            overrun     <= '0';
        elsif rising_edge(clk) then

            if run_serial = '1' then
                if cnt = C_N_MM_PSC-1 then
                    -- stop at the end
                    run_serial <= '0';
                else