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Commit faffd573 authored by BRONES Romain's avatar BRONES Romain
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Merge remote-tracking branch 'fix_uncontinuous' 

* Fix the packeter to generate continuous stream.
parents ddc189b8 da084f23
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hdl/ccn_pack.vhd
+ 3
− 3
View file @ faffd573
......@@ -292,7 +292,7 @@ begin
----------
fifo_tuser(0) <= or_reduce(fifo_tuser_slv);
inst_fifo: entity work.ccn_axis_fifo_frame
inst_fifo: entity work.ccn_axis_fifo_pframe
port map(
s_axis_aresetn => aresetn,
s_axis_aclk => aclk,
......@@ -324,7 +324,7 @@ begin
end if;
end process p_fsm_sync;
p_fsm_comb:process(fsm_state, packeter_run, new_seq, pkt_cnt_zero, pkt_ix_tready, frame_timeout)
p_fsm_comb:process(fsm_state, packeter_run, new_seq, pkt_cnt_zero, pkt_ix_tready, pkt_ix_tvalid, frame_timeout)
begin
case fsm_state is
when STANDBY =>
......@@ -361,7 +361,7 @@ begin
fsm_state_next <= ERR_SEQ;
elsif frame_timeout = '1' then
fsm_state_next <= ERR_TO;
elsif pkt_cnt_zero = '1' and pkt_ix_tready = '1' then
elsif pkt_cnt_zero = '1' and pkt_ix_tready = '1' and pkt_ix_tvalid = '1' then
fsm_state_next <= STANDBY;
else
fsm_state_next <= RUN;
......
sim/gen_testfile.py
+ 40
− 6
View file @ faffd573
import numpy as np
def genin():
# 3x 32bits words in hex
return "{:08X}{:08X}{:08X}".format(*[np.random.randint(0,2**32-1) for i in range(3)])
# BPM data per sequence
bps=10
# Number of sequence
nseq=13
# Generate a list of 16 bits words, 3 dimensions
seqdata = np.random.randint(0,2**16-1, (nseq,bps,5))
# Flatten last dimension, remove first sequence
seqframe = seqdata.reshape(nseq, bps*5)[1:]
# extend to multiple of 64 bits frames
seqframe = np.hstack((seqframe, np.zeros((nseq-1, int(np.ceil(bps*5/4))*4 - bps*5), dtype=int)))
# Reshape to 64 bits words
seqframe = seqframe.reshape(nseq-1, seqframe.shape[1]//4, 4)
# Generate input file
fp = open("testinput_001.txt", 'w')
for S, sdata in zip(range(nseq), seqdata):
for b, bdata in zip(range(bps), sdata):
fp.write("{:02X} ".format(S))
fp.write(("{:04X}"*5).format(*bdata[::-1]))
fp.write("\n")
fp.close()
for S in range(10):
for i in range(10):
fp.write("{:02X} {}\n".format(S, genin()))
# Generate frame file (for check)
fp = open("testframe_001.txt", 'w')
for sdata in seqframe:
for wdata in sdata:
fp.write(("{:04X}"*4).format(*wdata[::-1]))
fp.write("\n")
fp.close()
# Generate input file
fp = open("testoutput_001.txt", 'w')
for S, sdata in zip(range(nseq-1), seqdata[2:]):
for b, bdata in zip(range(bps), sdata):
fp.write("{:02X} ".format(S+1))
fp.write(("{:04X}"*5).format(*bdata[::-1]))
fp.write("\n")
fp.close()
sim/simulate.tcl
+ 15
− 2
View file @ faffd573
......@@ -3,14 +3,27 @@ create_project sim_packeter simproj
set_property source_mgmt_mode All [current_project]
read_vhdl {hdl/ccn_pos_unpack.vhd hdl/comcellnode_packeter.vhd sim/tb_ccn.vhd}
read_vhdl -vhdl2008 {sim/tb_ccn.vhd}
read_vhdl {hdl/ccn_unpack.vhd hdl/ccn_pack.vhd}
read_vhdl {hdl/pkg_bpmpacket_stream.vhd}
add_files -fileset sim_1 {sim/testinput_001.txt sim/testframe_001.txt sim/testoutput_001.txt }
set CCN_DPKT_W 80
set CCN_UPKT_W 80
set CCN_DPKT_TU_W 8
set CCN_UPKT_TU_W 8
set CCN_FRAME_W 64
set CCN_FRAME_HEADER_W 192
source tcl/generate_axis.tcl
update_compile_order -fileset sim_1
launch_simulation
close_wave_config
open_wave_config sim/tb_comcellnode_packeter.wcfg
open_wave_config sim/tb_ccn_global.wcfg
open_wave_config sim/tb_ccn_pack.wcfg
open_wave_config sim/tb_ccn_unpack.wcfg
restart
run 10 us
sim/tb_ccn.vhd
+ 103
− 4
View file @ faffd573
......@@ -22,7 +22,7 @@ architecture testbench of tb_ccn is
constant IPKT_TDATA_W : natural := 80;
constant IPKT_TUSER_W : natural := 8;
constant OPKT_TDATA_W : natural := 80;
constant OPKT_TUSER_W : natural := 1;
constant OPKT_TUSER_W : natural := 8;
constant FRAME_TDATA_W : natural := 64;
constant FRAME_TUSER_W : natural := 1;
......@@ -181,6 +181,7 @@ begin
m_axis_tready => tb_m_axis_tready,
m_axis_tdata => tb_m_axis_tdata,
m_axis_tkeep => tb_m_axis_tkeep,
m_axis_tuser => tb_m_axis_tuser,
m_axis_tlast => tb_m_axis_tlast
);
......@@ -302,21 +303,119 @@ begin
-- RX STREAM --
---------------
p_rx_recv:process
file testoutput : TEXT open READ_MODE is "testoutput_001.txt";
variable linenum : natural :=0;
variable text_line : line;
variable readok : boolean;
variable vr_tuser : std_logic_vector(OPKT_TUSER_W-1 downto 0);
variable vr_tdata : std_logic_vector(OPKT_TDATA_W-1 downto 0);
begin
while true loop
if not rx_recv then
tb_m_axis_tready <= '0';
wait until rx_recv and rising_edge(tb_m_clk);
wait until rx_recv and rising_edge(tb_clk);
end if;
tb_m_axis_tready <= '1';
wait until rising_edge(tb_m_clk) and tb_m_axis_tvalid ='1';
wait until rising_edge(tb_clk) and tb_m_axis_tvalid ='1';
tb_m_axis_tready <= '0';
if endfile(testoutput) then
report "End of file reached." severity warning;
exit;
end if;
readline(testoutput, text_line);
linenum := linenum+1;
hread(text_line, vr_tuser, readok);
assert readok
report "Read 'tuser' failed for line: " & integer'image(linenum) severity failure;
hread(text_line, vr_tdata, readok);
assert readok
report "Read 'tdata' failed for line: " & integer'image(linenum) severity failure;
assert tb_m_axis_tuser = vr_tuser
report "Packet output tuser check mismatch. Got " &
to_hex_string(tb_m_axis_tuser) & " ; Expected " & to_hex_string(vr_tuser)
severity warning;
assert tb_m_axis_tdata = vr_tdata
report "Packet output tdata check mismatch. Got " &
to_hex_string(tb_m_axis_tdata) & " ; Expected " & to_hex_string(vr_tdata)
severity warning;
for I in 1 to RX_COOLDOWN loop
wait until rising_edge(tb_m_clk);
wait until rising_edge(tb_clk);
end loop;
end loop;
end process p_rx_recv;
------------------
-- FRAME STREAM --
------------------
p_frame_stream:process
file testframe : TEXT open READ_MODE is "testframe_001.txt";
variable linenum : natural :=0;
variable text_line : line;
variable readok : boolean;
variable vr_tdata : std_logic_vector(FRAME_TDATA_W-1 downto 0);
variable masked_tdata : std_logic_vector(FRAME_TDATA_W-1 downto 0);
variable vr_cnt : natural := 0;
begin
while true loop
wait until
(rising_edge(tb_m_clk) and
eth_axis_tvalid = '1' and
eth_axis_tready = '1');
for I in 0 to FRAME_TDATA_W/8-1 loop
if eth_axis_tkeep(I) = '1' then
masked_tdata((I+1)*8-1 downto I*8) := eth_axis_tdata((I+1)*8-1 downto I*8);
else
masked_tdata((I+1)*8-1 downto I*8) := (others => '0');
end if;
end loop;
if vr_cnt > 2 then
if endfile(testframe) then
report "End of file reached." severity warning;
exit;
end if;
readline(testframe, text_line);
linenum := linenum+1;
hread(text_line, vr_tdata, readok);
assert readok
report "Read 'tdata' failed for line: " & integer'image(linenum) severity failure;
assert masked_tdata = vr_tdata
report "Frame check mismatch. Got " & to_hex_string(masked_tdata) & " ; Expected " & to_hex_string(vr_tdata)
severity warning;
if eth_axis_tlast = '1' then
vr_cnt := 0;
end if;
else
vr_cnt := vr_cnt+1;
end if;
end loop;
end process;
---------------------
-- TIMEREF COUNTER --
---------------------
......
sim/tb_ccn_pack.wcfg
+ 65
− 5
View file @ faffd573
......@@ -11,15 +11,15 @@
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="290fs"></ZoomStartTime>
<ZoomEndTime time="947291fs"></ZoomEndTime>
<Cursor1Time time="278290fs"></Cursor1Time>
<ZoomStartTime time="355363fs"></ZoomStartTime>
<ZoomEndTime time="1310364fs"></ZoomEndTime>
<Cursor1Time time="1440000fs"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="276"></NameColumnWidth>
<ValueColumnWidth column_width="273"></ValueColumnWidth>
<ValueColumnWidth column_width="265"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="27" />
<WVObjectSize size="42" />
<wvobject fp_name="divider58" type="divider">
<obj_property name="label">AXIS input</obj_property>
<obj_property name="DisplayName">label</obj_property>
......@@ -108,6 +108,14 @@
<obj_property name="label">INTERCO</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_ccn/inst_dut_pack/inst_interco/S00_AXIS_TVALID">
<obj_property name="ElementShortName">S00_AXIS_TVALID</obj_property>
<obj_property name="ObjectShortName">S00_AXIS_TVALID</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_ccn/inst_dut_pack/inst_interco/S00_AXIS_TREADY">
<obj_property name="ElementShortName">S00_AXIS_TREADY</obj_property>
<obj_property name="ObjectShortName">S00_AXIS_TREADY</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_ccn/inst_dut_pack/pkt_ix_tdata">
<obj_property name="ElementShortName">pkt_ix_tdata[79:0]</obj_property>
<obj_property name="ObjectShortName">pkt_ix_tdata[79:0]</obj_property>
......@@ -128,4 +136,56 @@
<obj_property name="ElementShortName">pkt_ix_tvalid</obj_property>
<obj_property name="ObjectShortName">pkt_ix_tvalid</obj_property>
</wvobject>
<wvobject fp_name="divider269" type="divider">
<obj_property name="label">OUTPUT FIFO</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_ccn/inst_dut_pack/inst_fifo/s_axis_tvalid">
<obj_property name="ElementShortName">s_axis_tvalid</obj_property>
<obj_property name="ObjectShortName">s_axis_tvalid</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_ccn/inst_dut_pack/inst_fifo/s_axis_tready">
<obj_property name="ElementShortName">s_axis_tready</obj_property>
<obj_property name="ObjectShortName">s_axis_tready</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_ccn/inst_dut_pack/inst_fifo/s_axis_tdata">
<obj_property name="ElementShortName">s_axis_tdata[63:0]</obj_property>
<obj_property name="ObjectShortName">s_axis_tdata[63:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_ccn/inst_dut_pack/inst_fifo/s_axis_tkeep">
<obj_property name="ElementShortName">s_axis_tkeep[7:0]</obj_property>
<obj_property name="ObjectShortName">s_axis_tkeep[7:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_ccn/inst_dut_pack/inst_fifo/s_axis_tlast">
<obj_property name="ElementShortName">s_axis_tlast</obj_property>
<obj_property name="ObjectShortName">s_axis_tlast</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_ccn/inst_dut_pack/inst_fifo/s_axis_tuser">
<obj_property name="ElementShortName">s_axis_tuser[0:0]</obj_property>
<obj_property name="ObjectShortName">s_axis_tuser[0:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_ccn/inst_dut_pack/inst_fifo/m_axis_tvalid">
<obj_property name="ElementShortName">m_axis_tvalid</obj_property>
<obj_property name="ObjectShortName">m_axis_tvalid</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_ccn/inst_dut_pack/inst_fifo/m_axis_tready">
<obj_property name="ElementShortName">m_axis_tready</obj_property>
<obj_property name="ObjectShortName">m_axis_tready</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_ccn/inst_dut_pack/inst_fifo/m_axis_tdata">
<obj_property name="ElementShortName">m_axis_tdata[63:0]</obj_property>
<obj_property name="ObjectShortName">m_axis_tdata[63:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_ccn/inst_dut_pack/inst_fifo/m_axis_tkeep">
<obj_property name="ElementShortName">m_axis_tkeep[7:0]</obj_property>
<obj_property name="ObjectShortName">m_axis_tkeep[7:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_ccn/inst_dut_pack/inst_fifo/m_axis_tlast">
<obj_property name="ElementShortName">m_axis_tlast</obj_property>
<obj_property name="ObjectShortName">m_axis_tlast</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_ccn/inst_dut_pack/inst_fifo/m_axis_tuser">
<obj_property name="ElementShortName">m_axis_tuser[0:0]</obj_property>
<obj_property name="ObjectShortName">m_axis_tuser[0:0]</obj_property>
</wvobject>
</wave_config>
tcl/generate_axis.tcl
+ 19
− 5
View file @ faffd573
......@@ -92,6 +92,23 @@ set_property -dict [list \
set_property GENERATE_SYNTH_CHECKPOINT 0 [get_files $xcipath]
# GENERATE AXIS FRAME FIFO
set xcipath [create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name ccn_axis_fifo_pframe]
set_property -dict [list \
CONFIG.TDATA_NUM_BYTES [expr $CCN_FRAME_W/8] \
CONFIG.TUSER_WIDTH {1} \
CONFIG.FIFO_DEPTH {256} \
CONFIG.FIFO_MODE {2} \
CONFIG.IS_ACLK_ASYNC {1} \
CONFIG.SYNCHRONIZATION_STAGES {3} \
CONFIG.HAS_TKEEP {1} \
CONFIG.HAS_TLAST {1} \
CONFIG.HAS_PROG_EMPTY {0} \
] [get_ips ccn_axis_fifo_pframe]
set_property GENERATE_SYNTH_CHECKPOINT 0 [get_files $xcipath]
####################
## CCN UNPACK IPS ##
####################
......@@ -110,19 +127,16 @@ set_property -dict [list \
set_property GENERATE_SYNTH_CHECKPOINT 0 [get_files $xcipath]
#########################
## CCN PACK/UNPACK IPS ##
#########################
# GENERATE AXIS FRAME FIFO
set xcipath [create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name ccn_axis_fifo_frame]
set_property -dict [list \
CONFIG.TDATA_NUM_BYTES [expr $CCN_FRAME_W/8] \
CONFIG.TUSER_WIDTH {1} \
CONFIG.FIFO_DEPTH {256} \
CONFIG.FIFO_DEPTH {64} \
CONFIG.FIFO_MODE {1} \
CONFIG.IS_ACLK_ASYNC {1} \
CONFIG.SYNCHRONIZATION_STAGES {3} \
CONFIG.HAS_TKEEP {1} \
CONFIG.HAS_TLAST {1} \
CONFIG.HAS_PROG_EMPTY {0} \
......
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