Change top level AXI port

* Use DESYRDL record

hdl/top_ccn_packeter.vhd

@@ -28,25 +28,8 @@ entity top_ccn_packeter is
 
         -- AXI-MM Status and Config
         aclk                        : in std_logic;
-        s_axi_awaddr                : in std_logic_vector(C_ADDR_WIDTH-1 downto 0);
-        s_axi_awprot                : in std_logic_vector(2 downto 0);
-        s_axi_awvalid               : in std_logic;
-        s_axi_wdata                 : in std_logic_vector(C_DATA_WIDTH-1 downto 0);
-        s_axi_wstrb                 : in std_logic_vector(C_DATA_WIDTH/8-1 downto 0);
-        s_axi_wvalid                : in std_logic;
-        s_axi_bready                : in std_logic;
-        s_axi_araddr                : in std_logic_vector(C_ADDR_WIDTH-1 downto 0);
-        s_axi_arprot                : in std_logic_vector(2 downto 0);
-        s_axi_arvalid               : in std_logic;
-        s_axi_rready                : in std_logic;
-        s_axi_awready               : out std_logic;
-        s_axi_wready                : out std_logic;
-        s_axi_bresp                 : out std_logic_vector(1 downto 0);
-        s_axi_bvalid                : out std_logic;
-        s_axi_arready               : out std_logic;
-        s_axi_rdata                 : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
-        s_axi_rresp                 : out std_logic_vector(1 downto 0);
-        s_axi_rvalid                : out std_logic;
+        s_axi_m2s                   : in t_ccn_packeter_m2s;
+        s_axi_s2m                   : out t_ccn_packeter_s2m;
 
         -- AXIS Packet input
         s_axis_tdata                : in std_logic_vector(G_S_TDATA_W-1 downto 0);
@@ -84,8 +67,6 @@ architecture rtl of top_ccn_packeter is
     -- AXIMM
     signal addrmap_i           : t_addrmap_ccn_packeter_in;
     signal addrmap_o           : t_addrmap_ccn_packeter_out;
-    signal s_axi_m2s           : t_ccn_packeter_m2s;
-    signal s_axi_s2m           : t_ccn_packeter_s2m;
 
     signal areset              : std_logic;
 
@@ -111,29 +92,6 @@ begin
     mac_dst  <= addrmap_o.mac_dst_msb.data.data & addrmap_o.mac_dst_lsb.data.data;
     mac_src  <= addrmap_o.mac_src_msb.data.data & addrmap_o.mac_src_lsb.data.data;
 
-    -- Mapping interface signals
-    s_axi_m2s.awaddr(C_ADDR_WIDTH-1 downto 0)  <= s_axi_awaddr;
-    s_axi_m2s.awaddr(C_AXI4L_ADDR_WIDTH-1 downto C_ADDR_WIDTH)  <= (others => '0');
-    s_axi_m2s.awprot  <= s_axi_awprot;
-    s_axi_m2s.awvalid <= s_axi_awvalid;
-    s_axi_m2s.wdata   <= s_axi_wdata;
-    s_axi_m2s.wstrb   <= s_axi_wstrb;
-    s_axi_m2s.wvalid  <= s_axi_wvalid;
-    s_axi_m2s.bready  <= s_axi_bready;
-    s_axi_m2s.araddr(C_ADDR_WIDTH-1 downto 0)  <= s_axi_araddr;
-    s_axi_m2s.araddr(C_AXI4L_ADDR_WIDTH-1 downto C_ADDR_WIDTH)  <= (others => '0');
-    s_axi_m2s.arprot  <= s_axi_arprot;
-    s_axi_m2s.arvalid <= s_axi_arvalid;
-    s_axi_m2s.rready  <= s_axi_rready;
-    s_axi_awready <= s_axi_s2m.awready;
-    s_axi_wready  <= s_axi_s2m.wready;
-    s_axi_bresp   <= s_axi_s2m.bresp;
-    s_axi_bvalid  <= s_axi_s2m.bvalid;
-    s_axi_arready <= s_axi_s2m.arready;
-    s_axi_rdata   <= s_axi_s2m.rdata;
-    s_axi_rresp   <= s_axi_s2m.rresp;
-    s_axi_rvalid  <= s_axi_s2m.rvalid;
-
     ----------
     -- CORE --
     ----------

hdl/top_ccn_unpacketer.vhd

@@ -28,25 +28,8 @@ entity top_ccn_unpacketer is
 
         -- AXI-MM Status and Config
         aclk                        : in std_logic;
-        s_axi_awaddr                : in std_logic_vector(C_ADDR_WIDTH-1 downto 0);
-        s_axi_awprot                : in std_logic_vector(2 downto 0);
-        s_axi_awvalid               : in std_logic;
-        s_axi_wdata                 : in std_logic_vector(C_DATA_WIDTH-1 downto 0);
-        s_axi_wstrb                 : in std_logic_vector(C_DATA_WIDTH/8-1 downto 0);
-        s_axi_wvalid                : in std_logic;
-        s_axi_bready                : in std_logic;
-        s_axi_araddr                : in std_logic_vector(C_ADDR_WIDTH-1 downto 0);
-        s_axi_arprot                : in std_logic_vector(2 downto 0);
-        s_axi_arvalid               : in std_logic;
-        s_axi_rready                : in std_logic;
-        s_axi_awready               : out std_logic;
-        s_axi_wready                : out std_logic;
-        s_axi_bresp                 : out std_logic_vector(1 downto 0);
-        s_axi_bvalid                : out std_logic;
-        s_axi_arready               : out std_logic;
-        s_axi_rdata                 : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
-        s_axi_rresp                 : out std_logic_vector(1 downto 0);
-        s_axi_rvalid                : out std_logic;
+        s_axi_m2s                   : in t_ccn_unpacketer_m2s;
+        s_axi_s2m                   : out t_ccn_unpacketer_s2m;
 
         -- AXIS Frame input
         s_axis_clk                  : in std_logic; -- Only S_AXIS signals on this clk domain
@@ -84,8 +67,6 @@ architecture struct of top_ccn_unpacketer is
     -- AXIMM
     signal addrmap_i           : t_addrmap_ccn_unpacketer_in;
     signal addrmap_o           : t_addrmap_ccn_unpacketer_out;
-    signal s_axi_m2s           : t_ccn_unpacketer_m2s;
-    signal s_axi_s2m           : t_ccn_unpacketer_s2m;
 
     signal areset              : std_logic;
 
@@ -111,29 +92,6 @@ begin
     mac_dst  <= addrmap_o.mac_dst_msb.data.data & addrmap_o.mac_dst_lsb.data.data;
     mac_src  <= addrmap_o.mac_src_msb.data.data & addrmap_o.mac_src_lsb.data.data;
 
-    -- Mapping interface signals
-    s_axi_m2s.awaddr(C_ADDR_WIDTH-1 downto 0)  <= s_axi_awaddr;
-    s_axi_m2s.awaddr(C_AXI4L_ADDR_WIDTH-1 downto C_ADDR_WIDTH)  <= (others => '0');
-    s_axi_m2s.awprot  <= s_axi_awprot;
-    s_axi_m2s.awvalid <= s_axi_awvalid;
-    s_axi_m2s.wdata   <= s_axi_wdata;
-    s_axi_m2s.wstrb   <= s_axi_wstrb;
-    s_axi_m2s.wvalid  <= s_axi_wvalid;
-    s_axi_m2s.bready  <= s_axi_bready;
-    s_axi_m2s.araddr(C_ADDR_WIDTH-1 downto 0)  <= s_axi_araddr;
-    s_axi_m2s.araddr(C_AXI4L_ADDR_WIDTH-1 downto C_ADDR_WIDTH)  <= (others => '0');
-    s_axi_m2s.arprot  <= s_axi_arprot;
-    s_axi_m2s.arvalid <= s_axi_arvalid;
-    s_axi_m2s.rready  <= s_axi_rready;
-    s_axi_awready <= s_axi_s2m.awready;
-    s_axi_wready  <= s_axi_s2m.wready;
-    s_axi_bresp   <= s_axi_s2m.bresp;
-    s_axi_bvalid  <= s_axi_s2m.bvalid;
-    s_axi_arready <= s_axi_s2m.arready;
-    s_axi_rdata   <= s_axi_s2m.rdata;
-    s_axi_rresp   <= s_axi_s2m.rresp;
-    s_axi_rvalid  <= s_axi_s2m.rvalid;
-
 
     ----------
     -- CORE --