chore:Update documentation, update module ID

doc/main.adoc

-= COMCELLNODE BPM PACKETER module documentation
+= COMCELLNODE PACKET module documentation
+
+|===
+| Packeter Module ID | 0x507E1743 | (1350440771)
+| Unpacketer Module ID | 0x507E1746 | (1350440774)
+|===
+
 
 // ================================================================================
 == Description
-This module generate Position Packets, embedded in Ethernet L2 Frames  ready to be processed by the Xilinx Ethernet Subsystem.
+
+This module contains blocs to allow communication between FOFB nodes.
+It provides a packeter which embeds packets in Ethernet L2 Frames ready to be processed by the Xilinx Ethernet Subsystem.
 (Only the Ethernet L2 CRC is missing, which is added by the IP).
+Symetrically, it provides a unpacketer, which retrieve data from packets in L2 frames, received from the Xilinx Ethernet Subsystem.
+_The Xilinx Ethernet Subsystem IP is included in the module CCN_ETHERNET_
+
+The packeter and unpacketer are generic.
+They can be configured to carry position or correction data.
+One just has to configure the data stream width.
+
+
+=== Packeter
+
+It receives a data stream from the application (i.e. from COMBPM module).
+
+The AXIS signals used are:
+
+* TDATA: contains the data, packed format depends on the user.
+* TUSER: contains a sequence number.
+* TVALID: Data strobe
+* TREADY: Data throthling from the module.
 
-It receives a BPM packet stream from the application (i.e. from COMBPM module and BPM packet filter).
-A new FA sequence is detected with the FA sequence number.
-A known number (indicated by CPU configuration) of BPM packets is included in the output packet.
+The packeter waits for a sequence number change to prepare a new packet.
+A known number (indicated by CPU configuration) of data words are included in the output packet.
 
 A header is appended to the transmitted data.
-It contains some parts of Ethernet Frame (as expected by Xilinx Ethernet Subsystem), concatenated with the Position Packet header (Timestamp, packet ID).
+It contains some parts of Ethernet Frame (as expected by Xilinx Ethernet Subsystem), concatenated with the timestamp and protocol ID.
 
 Error are raised when:
 
-- Supplementary BPM packets with same FA sequence number are received.
-- Timeout expecting new BPM packets.
+- Supplementary data words with same sequence number are received.
+- Timeout expecting next data words (incomplete packet).
 
+=== Unpacketer
+
+It receives L2 packets from the Ethernet IP.
+
+It simply removes the header, keeping the values in status register accessible from the AXI-MM.
+Then it changes the data width to get data word by data word transfer on the AXIS output.
 
 
 // ================================================================================
 == Overview
 
-=== Main operation: Top level
-
-This module works on the streaming BPM packets.
+=== Packeter
 
-* *Axis Register Slice*. Used to bufferize the incoming BPM packet.
+* *AXIS Register Slice*. Used to bufferize the incoming data words.
 Gives time to detect a new sequence and handle back pressure from the stream.
-Indeed, the register will hold the first BPM packet while the header is transmitted.
+Indeed, the register will hold the first data word while the header is transmitted.
 
-* *Detect BPM frame sequence*.
-Using the FA sequence number, it detects changes in it to synchronize the state machine to the begining of a FA frame.
+* *Detect frame sequence*.
+Using the sequence number, it detects changes in it to synchronize the state machine to the begining of a new packet.
 
-
-* *Pass or Dump*. Dump BPM packets when seeking for a FA frame begining.
+* *Pass or Dump*. Dump data words when seeking for a sequence begining.
 This handles the AXIS signaling to free the input register.
 
-* *Count BPM packet*. Programmed with the expected number of BPM packets, this decrement when a new BPM packet is added to the Ethernet output frame.
+* *Count BPM packet*. Programmed with the expected number of data words, this decrement when a new data word is added to the Ethernet output frame.
 
-* *Header*. Prepared header to transfer prior the first BPM packet.
-It is configured with MAC addresses, Frame length and receive a timestamp when the first BPM Packet reaches the input.
+* *Header*. Prepared header to transfer prior the first data word.
+It is configured with MAC addresses, Frame length and receive a timestamp when the first data word reaches the input.
 
 * *State Machine*.
 Coordinate the interconnexion, pass/dump.
-It detects erroneous situation (too many/few BPM packets).
+It detects erroneous situation (too many/few data words).
+
+.Basic overview of CCN packeter
+image::images/packeter_overview.svg[]
 
-.Basic overview of comcell bpmpacketer module
-image::images/overview.svg[]
+=== Unpacketer
 
+* *AXIS FIFO*. Used to bufferize the incoming stream and perform CDC.
+
+* *Header removal*. Based on a state machine, it removes the header while keeping the values in register ready to be read by the AXI-MM.
+  There it also checks the MAC addressed and protocol ID.
+
+* *AXIS Wconv*. Convert the remaining stream to proper data words.
+
+.Basic overview of CCN unpacketer
+image::images/unpacketer_overview.svg[]
 
 // ================================================================================
 == Details
 
-=== Structural schematic
+=== Packeter
 
 .Structural schematic of comcellnode bpmpacketer.
-image::images/schematic.svg[]
+image::images/packeter_schematic.svg[]
 
-=== State Machine
 
 .State machine
-image::images/fsm.svg[]
+image::images/packeter_fsm.svg[]
+
+=== Unpacketer
 
 // ================================================================================
 == Registers map
-include::regmap.adoc[]
+include::packeter_regmap.adoc[]
+include::unpacketer_regmap.adoc[]
 
 // ================================================================================
 == TODO/Future of this module
 
+* Output timestamps for latency computation ?.

rdl/ccn_packeter.rdl

 `include "ccn_packeter.vh"
 
+`define C_ID 0x507E1743
+
 addrmap ccn_packeter {
 
     desyrdl_generate_hdl = true;
     desyrdl_interface = "AXI4L";
 
+    reg {
+      desc="Module Identification Number";
+      default sw = r;
+      default hw = r;
+      field {} data[32] = `C_ID;
+    } ID @0x00;
+
     reg {
         desc="Module version.";
         field {hw=w;sw=r;} data[32];
-    } VERSION;
+    } VERSION @0x04;
 
     reg {
         desc="Ethernet MAC frame destination address. Least Significant Bytes.";

rdl/ccn_unpacketer.rdl

 `include "ccn_unpacketer.vh"
 
+`define C_ID 0x507E1746
+
 addrmap ccn_unpacketer {
 
     desyrdl_generate_hdl = true;
     desyrdl_interface = "AXI4L";
 
+    reg {
+      desc="Module Identification Number";
+      default sw = r;
+      default hw = r;
+      field {} data[32] = `C_ID;
+    } ID @0x00;
+
     reg {
         desc="Module version.";
         field {hw=w;sw=r;} data[32];
-    } VERSION;
+    } VERSION @0x04;
 
     reg {
         desc="Ethernet MAC frame destination address. Least Significant Bytes.";