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Commit 370d3b5e authored by BRONES Romain's avatar BRONES Romain
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Merge branch 'sim'

* Simulation was improved and is ready to be driven by fwk
* Fix tb_counter signal on the way
parents 9a722556 ef22e7b1
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...@@ -74,11 +74,11 @@ cseq = cseq[cseq['seqnum']!=1] ...@@ -74,11 +74,11 @@ cseq = cseq[cseq['seqnum']!=1]
#%% #%%
# Print to file # Print to file
with open("testinput_002.txt", 'w') as fp: with open("testinput.dat", 'w') as fp:
for d in sequences: for d in sequences:
fp.write("{:04X} {:04X}{:08X}{:08X}\n".format(*d)) fp.write("{:04X} {:04X}{:08X}{:08X}\n".format(*d))
with open("testoutput_002.txt", 'w') as fp: with open("testoutput.dat", 'w') as fp:
for d in cseq: for d in cseq:
fp.write("{:02X} {:04X}{:08X}{:08X}\n".format(*d)) fp.write("{:02X} {:04X}{:08X}{:08X}\n".format(*d))
...@@ -66,7 +66,7 @@ architecture testbench of tb_ccn is ...@@ -66,7 +66,7 @@ architecture testbench of tb_ccn is
signal tb_pack_mac_length : std_logic_vector(15 downto 0); signal tb_pack_mac_length : std_logic_vector(15 downto 0);
signal tb_pack_expect_pkt : std_logic_vector(7 downto 0); signal tb_pack_expect_pkt : std_logic_vector(7 downto 0);
signal tb_pack_timeout : std_logic_vector(15 downto 0); signal tb_pack_timeout : std_logic_vector(15 downto 0);
signal tb_pkt_rate_cnt : std_logic_vector(18 downto 0); signal tb_pkt_rate_cnt : std_logic_vector(23 downto 0);
-- Packeter status -- Packeter status
...@@ -224,7 +224,6 @@ begin ...@@ -224,7 +224,6 @@ begin
tb_unpack_mac_src <= (others => '0'); tb_unpack_mac_src <= (others => '0');
tb_unpack_mac_length <= (others => '0'); tb_unpack_mac_length <= (others => '0');
tb_unpack_enable <= '0'; tb_unpack_enable <= '0';
--tb_pkt_rate_cnt <= (others => '0');
wait for 4*PERIOD; wait for 4*PERIOD;
...@@ -252,7 +251,6 @@ begin ...@@ -252,7 +251,6 @@ begin
tb_pack_expect_pkt <= std_logic_vector(to_unsigned(10-1, tb_pack_expect_pkt'length)); tb_pack_expect_pkt <= std_logic_vector(to_unsigned(10-1, tb_pack_expect_pkt'length));
tb_pack_mac_length <= std_logic_vector(to_unsigned(10*10+10, tb_pack_mac_length'length)); tb_pack_mac_length <= std_logic_vector(to_unsigned(10*10+10, tb_pack_mac_length'length));
tb_unpack_mac_length<= std_logic_vector(to_unsigned(10*10+10, tb_pack_mac_length'length)); tb_unpack_mac_length<= std_logic_vector(to_unsigned(10*10+10, tb_pack_mac_length'length));
--tb_pkt_rate_cnt <= (others => '0');
wait until rising_edge(tb_clk); wait until rising_edge(tb_clk);
...@@ -275,7 +273,7 @@ begin ...@@ -275,7 +273,7 @@ begin
--------------- ---------------
p_tx_send:process p_tx_send:process
file testinput : TEXT open READ_MODE is "testinput.txt"; file testinput : TEXT open READ_MODE is "testinput.dat";
variable linenum : natural :=0; variable linenum : natural :=0;
variable text_line : line; variable text_line : line;
variable readok : boolean; variable readok : boolean;
...@@ -328,7 +326,7 @@ begin ...@@ -328,7 +326,7 @@ begin
--------------- ---------------
p_rx_recv:process p_rx_recv:process
file testoutput : TEXT open READ_MODE is "testoutput.txt"; file testoutput : TEXT open READ_MODE is "testoutput.dat";
variable linenum : natural :=0; variable linenum : natural :=0;
variable text_line : line; variable text_line : line;
variable readok : boolean; variable readok : boolean;
......
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testinput_002.txt
\ No newline at end of file
02 000DD3257C0CD2EAB242
02 000EE1539FD4EBF7F073
02 000F650AB0C6E1E463FF
02 0010A046E3C9BE897767
02 00116FD504DB15863D05
02 001229CAF7A45C20F46A
02 0013510E66118E7FAEE2
02 0014C06F16642358D0CC
02 0015C676DC8F4B149926
02 0016C1439185CDC81791
03 000D70D133708C2D116A
03 000EFC9D90AF3DB26E36
03 000FDB6F9C645F1A465E
03 001077602178C26B05F7
03 00118966137175AA0F99
03 0012F50E08A1869B4D19
03 0013554F2F87AC114788
03 00142C9ED6F8FE6B98AE
03 0015A0D18FEE8103ED4C
03 001660049CDC7F9A6FD9
04 000D31F2EEC4CAD05444
04 000EAB29923385328EFE
04 000FCFEF2DB8777DF26D
04 001080D8761EBC703069
04 001190218CA255DB0CF0
04 00128A5A1D0A0E9332A6
04 0013E282C9CB3D09080C
04 00147CFAA798A5C5B5A3
04 0015ECBCAB311BD07F51
04 001683E371EF85B0E608
05 000D2D8BF9DDBCC61A71
05 000E223BE3DE9690D996
05 000FC32F4FFE037380C0
05 0010E8F9069569F9A0EF
05 0011C48CDEB497AFB609
05 0012BF34206D199DADCA
05 00138FE3ED666096FF54
05 001489A44F8674AC1555
05 00155F37D508678259F3
05 00162DA68BC1FBE5EDBA
06 000DC1456A7B573093D1
06 000EA6FB0DE2EB3F982D
06 000F04BD44F91635AB40
06 00109B709938F401E538
06 0011B02F087E5B40DA1D
06 00123F31322952672F09
06 00131CA2351E6D12C172
06 0014A0D6CCBAC88DE9B1
06 0015828EC7DFF91D1470
06 0016E6B8E1D20777CF4C
07 000DDE1AC569DFBC1DF8
07 000E01A3BC4C6464A53A
07 000FAA350D996B9B603C
07 0010630578FEEE122ABD
07 00110079D3E26826512A
07 00129A43995741C874FC
07 0013A886B00D9291FFC5
07 00145228A4E58637BD5C
07 001593B6312D4F38CD9B
07 001629D8A132B53ED66C
08 000D5265DC6AA4EA2ECA
08 000E9FD5B616827B05DD
08 000F9925F5F55C0303AA
08 0010183838103BD281DB
08 001179D47A0EE1B9BC85
08 0012BEC2A5BD6B0FD386
08 0013877A43F84A030FA9
08 00148BF48FD9215F58E2
08 0015C473C75A09605201
08 001640539E604D942A6A
09 000DB82A9145F51665A4
09 000E92FB75555DDC189B
09 000FAC5EF334A0C15A27
09 001058399F87E031E477
09 0011A39FF73CAADA41EE
09 0012076628F4F4F5E543
09 0013D2AD73224BB4E045
09 00143F503CDB51C7C4BB
09 0015AC2A97367B423EFA
09 0016817FA45E33C2275E
0A 000D2BB83D6C6CE31CCE
0A 000EF8F61E46D705814C
0A 000FC9D43A43CC5C5261
0A 0010F49A6356E8337D6E
0A 0011E253DC9889DA9B06
0A 0012E748E08090B1D8C7
0A 00138F2BFC56F47BE5B5
0A 001493A45AA60CFFE3E4
0A 00158FFA5AD18FBD0031
0A 0016B9E6F9B503A9C807
0B 000DCAEDFF0F02E971A7
0B 000E77B0EF97EBB2352C
0B 000FE483C37BB722405D
0B 0010F5142A7EA5AA8D26
0B 00114A1C3FACDAF26898
0B 001235AD84940526C890
0B 0013A20390E60E9E2E91
0B 00145A0C3BFDB8C62D04
0B 00153650589B9EC0470D
0B 001602DA2E8FFF9EDFB4
0C 000D3F105C1A2A724E80
0C 000E796EB977FA914C39
0C 000F448C8FC2C0ED1D71
0C 00107C65F4A97BD3E397
0C 0011093D543511205AD3
0C 00128130945275D0C21F
0C 00133B82900DB6F4DBDC
0C 00141505BE790CDC3FEC
0C 0015156062EBC3B69857
0C 00166F2AFB92A4D2E225
1B 000D857622953C9E3504
1B 000EEC798E3B4ACB536C
1B 000F1FEABD60D49E8A3A
1B 00102B82BBBAAA169678
1B 0011360BE54B6EE13FF5
1B 0012644C4B0AA9646D81
1B 0013450DC3F18A73249E
1B 0014799811C8FADA07B1
1B 00152894AD777F911412
1B 0016E1404C7274CB6363
1C 000D71889DEA0C21F637
1C 000E048E328C1334E5EF
1C 000F5BA0E8E0AB70B644
1C 0010A36DBB113B603B5B
1C 00113A30D45F916601E8
1C 0012D53ED26510150596
1C 00139DB341C7E753DCCF
1C 00141B28E82F14AA7CC4
1C 00150F5F9CA4846DA763
1C 00162E9E82A030D8EB47
1D 000D61398A8F4745BB1C
1D 000E2FE19E0DE6C983A8
1D 000FB9D6F2EB51766EA6
1D 0010465B5BAEEA10CA6A
1D 00113A7F065DA3E4DAF8
1D 001236FA5539F5AE616E
1D 001346D4504511A282C8
1D 00144D6395095D65E977
1D 0015653AF08208717A0E
1D 00169A33507466F9A8F2
1E 000D4724BC8E79A1CB0F
1E 000E39434AB456571F25
1E 000FFB91B50420B659A8
1E 00103CDE9B2AE2DB5D00
1E 00116D169A088D4B8D62
1E 00122DE98107FB7AA505
1E 001318E5212C76E49C5B
1E 001473289BE8B8FAA818
1E 00150E288C723A545B39
1E 001611FA3759C70B1E5E
1F 000DE54E72428C541E3D
1F 000E166417B04FBB54CE
1F 000F89457F750DC5DA93
1F 0010DBC1C0975CCC283C
1F 001134F7D469FA4E56E1
1F 0012227918968F0D7AF6
1F 0013AE5C482E87FDA51B
1F 00149682D5D19FF0754C
1F 0015507732BB21E560DC
1F 0016BE2050E326E9E63C
20 000DB4B687E83B2ADD78
20 000E7116BD552F0CE48C
20 000FEEA679199D8CB4DF
20 001054EB3962D1FF8B77
20 00111157708E48C64792
20 0012FBF2D43E06F7BAD0
20 001386BEA71238340DAA
20 00146F35B7DD41CC17B4
20 00151D4E6E0423E23AB8
20 0016ECA32480E6724D87
21 000D8028EA8F00DFDB8D
21 000EE5AED199F002B73B
21 000F65561FCE3BCB19EF
21 0010E64D36EEA7B965FC
21 00110691F335A977B779
21 0012A8705AE07019EE96
21 0013A5D9440E868DFE69
21 0014B789CB17C8912E63
21 0015C3F7AC0C86BCA548
21 0016F75793320C319C44
22 000D935C89E78BCF828B
22 000E519DD8B5DA4500EC
22 000F728D16FD22B2EBA2
22 00100621B9DC64F0B952
22 00111F130414A456C101
22 00121907DABE7C6F411C
22 00136D70C7F6B542E9D7
22 001430267E33966D44D0
22 0015CFFF41E9D481362F
22 00165FF6F987527192DF
23 000D273F486D7987CDF9
23 000ED8648A3B2565FAA9
23 000FEEC7B2F35E1489E5
23 0010941C1B15B4D3A794
23 0011B02E9B0A10A03652
23 0012EF7E8BAAA5BC41AD
23 00130E148AD4BCB7E573
23 0014C66A9FE7D123930C
23 00153570B03485955F7C
23 00164A53B25FAED996C8
24 000D90BA6FD8077F9849
24 000ECBD8A6201F084710
24 000FCE27E40B52446980
24 0010BD1EB3E6D1A26CC4
24 0011795D039634D2C269
24 00125ECB99C30B0885DC
24 001398DC53A9FD8F5D94
24 0014B512A024A3C45CB3
24 0015E79E88068509E66F
24 0016989F0CE4450DCCF1
25 000D44167B0EE6441025
25 000ED91A945F6B9DBAA9
25 000F8AB26629D7EBFC81
25 00100488E5D7033956CF
25 00116D11BDF763C20520
25 0012594D795EA819ED5C
25 001351051189940429CB
25 0014B8BBE616B1EC8F04
25 00159D34B41D9E81D240
25 0016DC07A2F82712E70A
26 000D136AE35997E5C6C4
26 000E2B66D161A3A7C202
26 000F2AB1DADA3278AD3C
26 0010B233CBF56410B185
26 0011EEAFA12E69B40738
26 0012EE88B22B6808A9CB
26 00136D2E9101D765E735
26 00141EECD5F34F6C0746
26 00153AEB22FE9B37C364
26 00167A1A018986AC2DB1
35 000DB6D1625F3DC7C3BB
35 000E3320310BE01A3FA2
35 000FB6E37A74A68D6734
35 0010CF0430CCC19264E0
35 00118010FB0D8535BC4B
35 00120D2D05680076D4E1
35 00138CBB5BE42EE7D9D6
35 0014C79DA27248D393E5
35 00155A1AEAFD0A5FA996
35 0016DFA66E65E3064CDC
36 000D4108BB6F6A15DD0B
36 000EE26854233809EA50
36 000FC332E782A05F5852
36 0010BF37A578DD559016
36 001164C419E6D8AD2877
36 0012A000C3C7626980AA
36 00139E0665C4289D3712
36 0014BD98D23991EE174A
36 0015A102A35550D0E49F
36 0016B5E8000233E74E12
37 000DA86791E98185C2BC
37 000E015AEA98D76F0549
37 000F095D7E14A0298A04
37 00108E7DE54A668C7C7F
37 00116B521769F6F46634
37 0012E263E7FF4E46AAE9
37 0013F49601305C8E8EFA
37 00143F4D2B4C043E668D
37 0015BD791EC28882D5F2
37 00160BBCD513C6795836
38 000D166E831554F3B0DF
38 000EF5CC301B0DC7FC9B
38 000FA7CF4D52E78F734B
38 001082FBA9D2276D5198
38 0011BBD24F2CAF97B7F2
38 0012BDB46B3C59ADD7DD
38 0013E40382EB0C685080
38 001440C03CD83D8182EF
38 00155EA40D4717FA92A5
38 00160245CF45258D2128
39 000DF9D9D0A9A47EF76A
39 000ED1250A25292D113B
39 000F96C455610F7D5A4E
39 001094BEB983451BC134
39 0011346C3DE47FDBC598
39 00125D02440290EDD0D0
39 00139A818D0B52F00277
39 0014A83D60908844A838
39 001588DEB2CE23E4706D
39 00165E8A2C2D41557683
3A 000D1002BD636794ECD4
3A 000EB0AB6FB9E6D1100C
3A 000FEA6A039979367D66
3A 0010151D757000A527A7
3A 0011537BE25FC2DEDB13
3A 0012E7651221661249D4
3A 001311D4AFEF89CF2D80
3A 001475AB9A4591DE091F
3A 001553BB7466F296B3DB
3A 0016511494B61C2C1463
3B 000DC872B1B51AA70D88
3B 000EA261308ECF354C79
3B 000F15E4720F1CD4BC49
3B 0010C86FD115B15B6D0C
3B 0011C1879140B05C22B0
3B 00121C64618353B41856
3B 0013BE296A099D56FEBD
3B 0014880FFC1C37C68492
3B 0015147EC5D55C4DFD81
3B 0016173F778F5B718560
3C 000DA542A4DD9608F807
3C 000E58473C08CBB7A6C5
3C 000F896B3599B8AB5F3E
3C 0010AA17F06A9FE25A99
3C 0011B29D0B03DEDD8A32
3C 0012D789C8985394CB29
3C 0013EBA6BB8A2D62A700
3C 0014AEF6E20762508999
3C 001520D76D6DFBADBF55
3C 00168C1A22320C78664C
3D 000D68F642C266744FFA
3D 000E7D9A219AC5C7FDFD
3D 000FE81163161D2258AB
3D 0010EC1369C4C04629D0
3D 00117C2F5DD15F81575B
3D 00128B82E3A494C87A3F
3D 0013786114D21E243C2A
3D 0014889059CDB0004684
3D 00156DF89D266DFF4E78
3D 00160EF03A049691D53D
3E 000DE93DAF99B22BE7A1
3E 000ECBEE8495D6D6F486
3E 000F2EEE34A5C37447E8
3E 0010C556E4E104AECB2E
3E 0011749DEF8AF3D2073A
3E 0012BDD68F0189E9F968
3E 00138E4B819F444AFCA7
3E 0014D0B0C369F7B2893F
3E 00155F01CB3B029C5132
3E 00160462CA08E504B9D4
3F 000D519BE79AB45BC181
3F 000E0C1CF44E3960E24D
3F 000F9E090D7B49813510
3F 0010A661B3DAFB22E645
3F 001107E1C1C5BD3E29DD
3F 001224DD19F951E1404F
3F 001379C1F48A8E42D8B5
3F 0014237E469310170CE7
3F 0015A036379B69F1DDD3
3F 001611F295BE016D599E
40 000D38B55CCD52DDF980
40 000EBCF152E22B6503E8
40 000F21AC8C00704DD483
40 0010F7591B5F838D0C3D
40 00113E93F6581B6ABC12
40 0012AEA53F0F746A0FAF
40 0013D98F057323BB26A2
40 00147D85AD829DDF6C2F
40 0015B03514B028850584
40 00164619ACF6C881E3D2
testoutput_002.txt
\ No newline at end of file
...@@ -11,23 +11,27 @@ proc init {} { ...@@ -11,23 +11,27 @@ proc init {} {
variable CCN_UPKT_W variable CCN_UPKT_W
variable CCN_UPKT_TU_W variable CCN_UPKT_TU_W
fwfwk::printInfo "Generate simulation file"
} }
# ============================================================================== # ==============================================================================
proc setSources {} { proc setSources {} {
variable Vhdl variable Sources
# Generate VHDL package with mode version # Generate VHDL package with mode version
genModVerFile VHDL ../hdl/pkg_ccn_packet_version.vhd genModVerFile VHDL ../hdl/pkg_ccn_packet_version.vhd
lappend Vhdl ../hdl/pkg_ccn_packet_version.vhd lappend Sources {"../hdl/pkg_ccn_packet_version.vhd" "VHDL" }
lappend Sources {"../hdl/ccn_pack.vhd" "VHDL" }
lappend Sources {"../hdl/ccn_unpack.vhd" "VHDL" }
lappend Sources {"../hdl/top_ccn_packeter.vhd" "VHDL" }
lappend Sources {"../hdl/top_ccn_unpacketer.vhd" "VHDL" }
lappend Sources {"../sim/tb_ccn.vhd" "VHDL 2008" "" "simulation"}
lappend Sources {"../sim/testinput.dat" "" "" "simulation"}
lappend Sources {"../sim/testoutput.dat" "" "" "simulation"}
lappend Sources {"../sim/tb_ccn_global.wcfg" "" "" "simulation"}
lappend Vhdl ../hdl/ccn_pack.vhd
lappend Vhdl ../hdl/ccn_unpack.vhd
lappend Vhdl ../hdl/top_ccn_packeter.vhd
lappend Vhdl ../hdl/top_ccn_unpacketer.vhd
} }
...@@ -49,9 +53,9 @@ proc doOnCreate {} { ...@@ -49,9 +53,9 @@ proc doOnCreate {} {
variable CCN_FRAME_HEADER_W variable CCN_FRAME_HEADER_W
variable CCN_UPKT_W variable CCN_UPKT_W
variable Vhdl variable Sources
addSources Vhdl addSources Sources
source generate_axis.tcl source generate_axis.tcl
} }
...@@ -62,19 +66,7 @@ proc doOnBuild {} { ...@@ -62,19 +66,7 @@ proc doOnBuild {} {
# ============================================================================== # ==============================================================================
proc setSim {} { proc setSim {} {
variable SimTop
variable VhdlSim set SimTop tb_ccn
variable SimFiles
fwfwk::printInfo "Generate test input file..."
cd sim
exec python gen_testfile.py
lappend VhdlSim ../sim/tb_ccn.vhd
lappend SimFiles ../sim/testinput_001.txt
lappend SimFiles ../sim/tb_ccn_global.wcfg
addSources VhdlSim -fileset sim_1
addSources SimFiles -fileset sim_1
} }
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