feat(ccnpack): Add latch sequence registers

hdl/ccn_pack.vhd

@@ -23,11 +23,14 @@ entity ccn_pack is
         packet_timeout       : in std_logic_vector(15 downto 0);
         expect_pkt_cnt       : in std_logic_vector(7 downto 0);
         timeref              : in std_logic_vector(63 downto 0);
+        latch_seq            : in std_logic;
 
         -- Status
         status_err_seq       : out std_logic;
         status_err_timeout   : out std_logic;
         status_frame_count   : out std_logic_vector(31 downto 0);
+        latched_seq1         : out std_logic_vector(15 downto 0);
+        latched_seq2         : out std_logic_vector(15 downto 0);
 
         -- AXIS Packet input
         s_axis_tdata         : in std_logic_vector(G_S_TDATA_W-1 downto 0);
@@ -150,10 +153,18 @@ begin
             prev_seq_r          <= (others => '0');
             new_seq_valid_r     <= '0';
             m_tvalid_r          <= '0';
+            latched_seq1        <= (others => '0');
+            latched_seq2        <= (others => '0');
         elsif rising_edge(aclk) then
             if (pkt_reg_tvalid and pkt_reg_tready) = '1' then
                 prev_seq_r      <= pkt_reg_tuser;
                 new_seq_valid_r <= '1';
+
+                if latch_seq = '0' and (pkt_reg_tuser /= prev_seq_r) then
+                    latched_seq1    <= std_logic_vector(resize(unsigned(pkt_reg_tuser), 16));
+                    latched_seq2    <= std_logic_vector(resize(unsigned(prev_seq_r), 16));
+                end if;
+
             end if;
             m_tvalid_r          <= pkt_reg_tvalid;
         end if;

hdl/top_ccn_packeter.vhd

@@ -120,11 +120,14 @@ begin
         packet_timeout       => addrmap_o.timeout.data.data,
         expect_pkt_cnt       => addrmap_o.npacket.data.data,
         timeref              => timeref,
+        latch_seq            => addrmap_o.control.latchseq.data(0),
 
         -- Status
         status_err_seq       => s_err_seq,
         status_err_timeout   => s_err_timeout,
         status_frame_count   => addrmap_i.packeter_count.data.data,
+        latched_seq1         => addrmap_i.latched_seq1.data.data,
+        latched_seq2         => addrmap_i.latched_seq2.data.data,
 
         -- AXIS Packet input
         s_axis_tdata         => s_axis_tdata,

rdl/ccn_packeter.rdl

@@ -48,6 +48,7 @@ addrmap ccn_packeter {
         desc="Packeter control.";
         default hw=r; default sw=rw;
         field {desc="Enable the BPM packeter.";} ENABLE;
+        field {desc="Latch sequence registers";} LATCHSEQ;
     } CONTROL;
 
     reg {
@@ -79,4 +80,14 @@ addrmap ccn_packeter {
         field {desc="Start the BPM packeter.";} RESET;
     } RESET_ERROR;
 
+    reg {
+        desc="Latched sequence register 1";
+        field {hw=w; sw=r;} data[16];
+    } LATCHED_SEQ1;
+
+    reg {
+        desc="Latched sequence register 2";
+        field {hw=w; sw=r;} data[16];
+    } LATCHED_SEQ2;
+
 };