Skip to content
Snippets Groups Projects

Repository graph

You can move around the graph by using the arrow keys.
Select Git revision
  • 1cd250a401724f13e722f1170295419bc3f1278e
  • main default protected
  • bugfix_timeout
  • dev_header
  • dev_rbs
  • fix_uncontinuous
  • pck_cnter
  • sim
  • sim_ccn
  • 1.3
  • 1.2.1
  • 1.2
  • 1.1.0
  • 1.0.0
14 results
Created with Raphaël 2.2.025Mar24141076321Feb1917111076528Jan23161520Nov8Aug27Jun2030May2Feb8Jan519Dec1816Nov96Jun519Mar1Feb24Jan1022Nov7431Oct17141310647Sep25Aug19UDP HDR: fix bugsim_ccnsim_ccnUDP HDR: make it more generic for future useSIM: add udp header capability into TBRDL: remove ETH HEAD from CCN PACKadding UPD: bug fixed at synthesis leveladding UDP: bug fixed at make projectadd UDP headerWIP: add UDP header over Ethernet L2Slice Reg : change mode from lighted-weight to fully registerunpack: Add a WCONV at input to handle 8bits mode (used for sim)fix: Include again RX side on the simulationresolve merge in tb_ccnRevert "add unpackter"ccn_pack : set INT_FRAME_W as variablesimu: add tready driverdoc: udpated ccn_pack schematicold mode to lew modedev_headerdev_headerWIP: INT_FRAME_W define as variableWIP: add UDP headersim: Use generic, remove packagesccn_pack:comment generic G_COMTYPE/G_ETHstop unessecary track .lock filesim: fix data output filesim: Fix unused GENERICSsim: Add word counter in TBadd unpackterGENERIC : COMTYPE and ETH PROTOCOL not used anymoreSIM : correct CLK domain in TB + in CCN_packmodify wcfg (addding wcfg)force wconv tready valuerun SIM ok (fix minor bugs in WCONV gendev_rbsdev_rbsMerge branch 'dev_rbs' into simsimsimsim: fix testbenchfix TUSER in FIFOfix TKEEP bugMerge branch 'dev_rbs' into simfixed CCN pack minor bugssim: Add simulation sources for correction datasim: Increase generate test data fileWIP : modify internal AXIS IP chain to fit with output IP data width

The place to be for your source code