Skip to content
GitLab
Explore
Sign in
Register
Primary navigation
Search or go to…
Project
C
comcellnode_ethernet
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Iterations
Wiki
Requirements
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Locked files
Build
Pipelines
Jobs
Pipeline schedules
Test cases
Artifacts
Deploy
Releases
Package registry
Container registry
Model registry
Operate
Environments
Terraform modules
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Code review analytics
Issue analytics
Insights
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
GitLab community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
DG
FOFB
comcellnode_ethernet
Commits
ebe40241
Commit
ebe40241
authored
Oct 14, 2022
by
BRONES Romain
Browse files
Options
Downloads
Patches
Plain Diff
Small correction after RDL change.
* Also change the package version name and import it
parent
bb65f12c
No related branches found
No related tags found
No related merge requests found
Changes
2
Show whitespace changes
Inline
Side-by-side
Showing
2 changed files
hdl/top_comcellnode_ethernet.vhd
+15
-15
15 additions, 15 deletions
hdl/top_comcellnode_ethernet.vhd
tcl/main.tcl
+2
-1
2 additions, 1 deletion
tcl/main.tcl
with
17 additions
and
16 deletions
hdl/top_comcellnode_ethernet.vhd
+
15
−
15
View file @
ebe40241
...
...
@@ -77,7 +77,7 @@ begin
po_addrmap
=>
addrmap_o
);
addrmap_i
.
version
.
data
<=
C_VERSION
;
addrmap_i
.
version
.
data
.
data
<=
C_VERSION
;
--------------
-- ETHERNET --
...
...
@@ -94,13 +94,13 @@ begin
qpll0lock_in
=>
qpll0lock_in
,
qpll0reset_out
=>
qpll0reset_out
,
tx_clk_rst
=>
addrmap_o
.
eth_
gt_control
.
rst_tx_clk
.
data
(
0
),
rx_clk_rst
=>
addrmap_o
.
eth_
gt_control
.
rst_rx_clk
.
data
(
0
),
tx_data_rst
=>
addrmap_o
.
eth_
gt_control
.
rst_tx_data
.
data
(
0
),
rx_data_rst
=>
addrmap_o
.
eth_
gt_control
.
rst_rx_data
.
data
(
0
),
tx_rst
=>
addrmap_o
.
eth_
gt_control
.
rst_tx
.
data
(
0
),
rx_rst
=>
addrmap_o
.
eth_
gt_control
.
rst_rx
.
data
(
0
),
gt_loopback
=>
addrmap_o
.
eth_
gt_control
.
loopback
.
data
,
tx_clk_rst
=>
addrmap_o
.
gt_control
.
rst_tx_clk
.
data
(
0
),
rx_clk_rst
=>
addrmap_o
.
gt_control
.
rst_rx_clk
.
data
(
0
),
tx_data_rst
=>
addrmap_o
.
gt_control
.
rst_tx_data
.
data
(
0
),
rx_data_rst
=>
addrmap_o
.
gt_control
.
rst_rx_data
.
data
(
0
),
tx_rst
=>
addrmap_o
.
gt_control
.
rst_tx
.
data
(
0
),
rx_rst
=>
addrmap_o
.
gt_control
.
rst_rx
.
data
(
0
),
gt_loopback
=>
addrmap_o
.
gt_control
.
loopback
.
data
,
gt_rx_out_clk
=>
open
,
gt_tx_out_clk
=>
open
,
...
...
@@ -115,13 +115,13 @@ begin
sfp_tx_fault
=>
sfp_tx_fault
,
-- Status
tx_clk_active
=>
addrmap_i
.
eth_
gt_status
.
tx_clk_active
.
data
(
0
),
rx_clk_active
=>
addrmap_i
.
eth_
gt_status
.
rx_clk_active
.
data
(
0
),
gt_powergood
=>
addrmap_i
.
eth_
gt_status
.
powergood
.
data
(
0
),
cdr_stable
=>
addrmap_i
.
eth_
gt_status
.
cdr_stable
.
data
(
0
),
rx_los
=>
addrmap_i
.
eth_
gt_status
.
sfp_rx_los
.
data
(
0
),
mod_abs
=>
addrmap_i
.
eth_
gt_status
.
sfp_mod_abs
.
data
(
0
),
tx_fault
=>
addrmap_i
.
eth_
gt_status
.
sfp_tx_fault
.
data
(
0
),
tx_clk_active
=>
addrmap_i
.
gt_status
.
tx_clk_active
.
data
(
0
),
rx_clk_active
=>
addrmap_i
.
gt_status
.
rx_clk_active
.
data
(
0
),
gt_powergood
=>
addrmap_i
.
gt_status
.
powergood
.
data
(
0
),
cdr_stable
=>
addrmap_i
.
gt_status
.
cdr_stable
.
data
(
0
),
rx_los
=>
addrmap_i
.
gt_status
.
sfp_rx_los
.
data
(
0
),
mod_abs
=>
addrmap_i
.
gt_status
.
sfp_mod_abs
.
data
(
0
),
tx_fault
=>
addrmap_i
.
gt_status
.
sfp_tx_fault
.
data
(
0
),
-- AXIS
rx_axis_tvalid
=>
m_axis_rx_tvalid
,
...
...
This diff is collapsed.
Click to expand it.
tcl/main.tcl
+
2
−
1
View file @
ebe40241
...
...
@@ -15,10 +15,11 @@ proc setSources {} {
variable Verilog
# Generate VHDL package with modle version
genModVerFile VHDL ../hdl/pkg_comcellnode_version.vhd
genModVerFile VHDL ../hdl/pkg_comcellnode_
ethernet_
version.vhd
lappend Vhdl ../hdl/comcellnode_ethernet.vhd
lappend Vhdl ../hdl/top_comcellnode_ethernet.vhd
lappend Vhdl ../hdl/pkg_comcellnode_ethernet_version.vhd
lappend Verilog ../hdl/comcellnode_ethernet_reset_wrapper.v
...
...
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment