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Commit ebe40241 authored by BRONES Romain's avatar BRONES Romain
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Small correction after RDL change.

* Also change the package version name and import it
parent bb65f12c
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......@@ -77,7 +77,7 @@ begin
po_addrmap => addrmap_o
);
addrmap_i.version.data <= C_VERSION;
addrmap_i.version.data.data <= C_VERSION;
--------------
-- ETHERNET --
......@@ -94,13 +94,13 @@ begin
qpll0lock_in => qpll0lock_in,
qpll0reset_out => qpll0reset_out,
tx_clk_rst => addrmap_o.eth_gt_control.rst_tx_clk.data(0),
rx_clk_rst => addrmap_o.eth_gt_control.rst_rx_clk.data(0),
tx_data_rst => addrmap_o.eth_gt_control.rst_tx_data.data(0),
rx_data_rst => addrmap_o.eth_gt_control.rst_rx_data.data(0),
tx_rst => addrmap_o.eth_gt_control.rst_tx.data(0),
rx_rst => addrmap_o.eth_gt_control.rst_rx.data(0),
gt_loopback => addrmap_o.eth_gt_control.loopback.data,
tx_clk_rst => addrmap_o.gt_control.rst_tx_clk.data(0),
rx_clk_rst => addrmap_o.gt_control.rst_rx_clk.data(0),
tx_data_rst => addrmap_o.gt_control.rst_tx_data.data(0),
rx_data_rst => addrmap_o.gt_control.rst_rx_data.data(0),
tx_rst => addrmap_o.gt_control.rst_tx.data(0),
rx_rst => addrmap_o.gt_control.rst_rx.data(0),
gt_loopback => addrmap_o.gt_control.loopback.data,
gt_rx_out_clk => open,
gt_tx_out_clk => open,
......@@ -115,13 +115,13 @@ begin
sfp_tx_fault => sfp_tx_fault,
-- Status
tx_clk_active => addrmap_i.eth_gt_status.tx_clk_active.data(0),
rx_clk_active => addrmap_i.eth_gt_status.rx_clk_active.data(0),
gt_powergood => addrmap_i.eth_gt_status.powergood.data(0),
cdr_stable => addrmap_i.eth_gt_status.cdr_stable.data(0),
rx_los => addrmap_i.eth_gt_status.sfp_rx_los.data(0),
mod_abs => addrmap_i.eth_gt_status.sfp_mod_abs.data(0),
tx_fault => addrmap_i.eth_gt_status.sfp_tx_fault.data(0),
tx_clk_active => addrmap_i.gt_status.tx_clk_active.data(0),
rx_clk_active => addrmap_i.gt_status.rx_clk_active.data(0),
gt_powergood => addrmap_i.gt_status.powergood.data(0),
cdr_stable => addrmap_i.gt_status.cdr_stable.data(0),
rx_los => addrmap_i.gt_status.sfp_rx_los.data(0),
mod_abs => addrmap_i.gt_status.sfp_mod_abs.data(0),
tx_fault => addrmap_i.gt_status.sfp_tx_fault.data(0),
-- AXIS
rx_axis_tvalid => m_axis_rx_tvalid,
......
......@@ -15,10 +15,11 @@ proc setSources {} {
variable Verilog
# Generate VHDL package with modle version
genModVerFile VHDL ../hdl/pkg_comcellnode_version.vhd
genModVerFile VHDL ../hdl/pkg_comcellnode_ethernet_version.vhd
lappend Vhdl ../hdl/comcellnode_ethernet.vhd
lappend Vhdl ../hdl/top_comcellnode_ethernet.vhd
lappend Vhdl ../hdl/pkg_comcellnode_ethernet_version.vhd
lappend Verilog ../hdl/comcellnode_ethernet_reset_wrapper.v
......
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