Add documentation, update RDL

* Add version register.
* Add registers decription.
* Ad a small documentation.

README.adoc

+include::doc/main.adoc[]

doc/main.adoc

+= COMCELLNODE ETHERNET module documentation
+
+// ================================================================================
+== Description
+This module instantiate the Xilinx Ethernet Subsystem for 10 GbE communication.
+
+The GT wizard core is separated from the Ethernet Subsystem, to allow different transceivers form one quad to run different communication type (ie Gbe and COMBPM).
+
+
+// ================================================================================
+== Overview
+
+=== Main operation: Top level
+
+This module is mainly structural, connecting the IP blocks with the control and status of the AXI-MM interface.
+
+The QPLL core shall be instanciated by the application, providing a 156.25 MHz clock ref.
+
+.Basic overview of comcell ethernet module
+image::images/overview.svg[]
+
+
+// ================================================================================
+== Registers map
+include::regmap.adoc[]
+
+// ================================================================================
+== TODO/Future of this module
+

doc/regmap.adoc

+.Register
+[.tab-addr-reg,cols="5,1,1,2,1,9"]
+|===
+|Name | N | bits | type | RW | Description
+
+| VERSION                                  |    1 |   32 | uint |   RO | +++Module version.+++  
+| GT_CONTROL                               |    1 |    9 | uint |   RW | +++GT core control.+++   +
+- RST_TX_CLK [0:0] sw:RW uint : +++Reset transmitter clock.+++  +
+- RST_RX_CLK [1:1] sw:RW uint : +++Reset receiver clock.+++  +
+- RST_TX_DATA [2:2] sw:RW uint : +++Reset transmitter datapath.+++  +
+- RST_RX_DATA [3:3] sw:RW uint : +++Reset receiver datapath.+++  +
+- RST_TX [4:4] sw:RW uint : +++Global reset on transmitter.+++  +
+- RST_RX [5:5] sw:RW uint : +++Global reset on receiver.+++  +
+- LOOPBACK [8:6] sw:RW uint : +++Loopback on the GT. See Xilinx doc.+++   
+| GT_STATUS                                |    1 |    7 | uint |   RO | +++GT core status.+++   +
+- CDR_STABLE [0:0] sw:RO uint : +++Clock Data Recovery is stable.+++  +
+- SFP_RX_LOS [1:1] sw:RO uint : +++Receiver loss indicator on the SFP module.+++  +
+- SFP_MOD_ABS [2:2] sw:RO uint : +++SFP module is absent.+++  +
+- SFP_TX_FAULT [3:3] sw:RO uint : +++Transmitter fault on the SFP module.+++  +
+- TX_CLK_ACTIVE [4:4] sw:RO uint : +++Transmitter clock is active.+++  +
+- RX_CLK_ACTIVE [5:5] sw:RO uint : +++Receiver clock is active.+++  +
+- POWERGOOD [6:6] sw:RO uint : +++Powergood on GT core.+++   
+|=== 
+
+ 
+.External address maps
+[.tab-addr-ext,cols="3,1,1,1,7"]
+|===
+|Name | size | address | interface | Description
+
+| ETH                                      | 2336 | 0x00001000 | AXI4L | +++Xilinx Ethernet Subsystem registers.+++ 
+|===

hdl/top_comcellnode_ethernet.vhd

@@ -6,6 +6,8 @@ library desyrdl;
 use desyrdl.common.all;
 use desyrdl.pkg_comcellnode_ethernet.all;
 
+use work.pkg_comcellnode_ethernet_version.all;
+
 entity top_comcellnode_ethernet is
     port(
         aresetn                     : in std_logic;
@@ -75,6 +77,8 @@ begin
         po_addrmap  => addrmap_o
     );
 
+    addrmap_i.version.data  <= C_VERSION;
+
     --------------
     -- ETHERNET --
     --------------

rdl/comcellnode_ethernet.rdl

@@ -8,23 +8,46 @@ addrmap comcellnode_ethernet {
     xilinx_ethsubsyst ETH @0x1000;
 
     reg {
-        field {hw=r; sw=rw;} RST_TX_CLK;
-        field {hw=r; sw=rw;} RST_RX_CLK;
-        field {hw=r; sw=rw;} RST_TX_DATA;
-        field {hw=r; sw=rw;} RST_RX_DATA;
-        field {hw=r; sw=rw;} RST_TX;
-        field {hw=r; sw=rw;} RST_RX;
-        field {hw=r; sw=rw;} LOOPBACK[3];
-    } ETH_GT_CONTROL;
+        desc="Module version.";
+        field {hw=w;sw=r;} data[32];
+    } VERSION;
 
     reg {
-        field {hw=w; sw=r;} CDR_STABLE;
-        field {hw=w; sw=r;} SFP_RX_LOS;
-        field {hw=w; sw=r;} SFP_MOD_ABS;
-        field {hw=w; sw=r;} SFP_TX_FAULT;
-        field {hw=w; sw=r;} TX_CLK_ACTIVE;
-        field {hw=w; sw=r;} RX_CLK_ACTIVE;
-        field {hw=w; sw=r;} POWERGOOD;
-    } ETH_GT_STATUS;
+        desc="GT core control.";
+        default hw=r;default sw=rw;
+        field {desc="Reset transmitter clock.";
+        } RST_TX_CLK;
+        field {desc="Reset receiver clock.";
+        } RST_RX_CLK;
+        field {desc="Reset transmitter datapath.";
+        } RST_TX_DATA;
+        field {desc="Reset receiver datapath.";
+        } RST_RX_DATA;
+        field {desc="Global reset on transmitter.";
+        } RST_TX;
+        field {desc="Global reset on receiver.";
+        } RST_RX;
+        field {desc="Loopback on the GT. See Xilinx doc.";
+        } LOOPBACK[3];
+    } GT_CONTROL;
+
+    reg {
+        desc="GT core status.";
+        default hw=w;default sw=r;
+        field {desc="Clock Data Recovery is stable.";
+		} CDR_STABLE;
+        field {desc="Receiver loss indicator on the SFP module.";
+		} SFP_RX_LOS;
+        field {desc="SFP module is absent.";
+		} SFP_MOD_ABS;
+        field {desc="Transmitter fault on the SFP module.";
+		} SFP_TX_FAULT;
+        field {desc="Transmitter clock is active.";
+		} TX_CLK_ACTIVE;
+        field {desc="Receiver clock is active.";
+		} RX_CLK_ACTIVE;
+        field {desc="Powergood on GT core.";
+		} POWERGOOD;
+    } GT_STATUS;
 
 };

rdl/xilinx_ethsubsyst.rdl

@@ -3,6 +3,8 @@ addrmap xilinx_ethsubsyst {
     desyrdl_generate_hdl = false;
     desyrdl_interface = "AXI4L";
 
+    desc="Xilinx Ethernet Subsystem registers.";
+
 //===================
 	reg {
 		field {