Removing useless files

tcl/comcellnode.tcl

-# Source metadata
-set design "comcellnode"
-set top top_comcellnode
-set part "xczu11eg-ffvc1760-2L-e"
-
-# Create project
-set ip_project [create_project -name ${design} -part ${part} -in_memory ]
-set_property top ${top} [current_fileset]
-
-# Compilation order in auto
-set_property source_mgmt_mode All ${ip_project}
-
-# Read sources
-source tcl/sources.tcl
-
-# Generate Xilinx IP
-source tcl/generate_ethernet.tcl
-
-# Compile order to auto
-update_compile_order -fileset sources_1
-
-# Package project
-set ip_properties [ list \
-    vendor "synchrotron-soleil.fr" \
-    library "user" \
-    name ${design} \
-    version "1.0" \
-    taxonomy "/Communication_&_Networking/Serial_Interfaces" \
-    display_name "Cell node Communication" \
-    description "Embed ethernet IP to perform inter cellnode communication." \
-    vendor_display_name "Synchrotron SOLEIL" \
-    company_url "http://www.synchrotron-soleil.fr" \
-    ]
-
-set family_lifecycle [list \
-  zynquplus{${part}} Beta \
-]
-
-ipx::package_project
-set ip_core [ipx::current_core]
-set_property -dict ${ip_properties} ${ip_core}
-set_property SUPPORTED_FAMILIES ${family_lifecycle} ${ip_core}
-
-# Associate AX/AXIS interfaces and reset with clock
-# Done in VHDL file
-
-# Remove default address map
-ipx::remove_memory_map [lindex [split [ipx::get_memory_maps]] 2] [ipx::current_core]
-
-# Create Address map
-set s_axi_mm [ipx::add_memory_map s_axi_ctrl [ipx::current_core]]
-set_property slave_memory_map_ref s_axi_ctrl [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
-set_property ENABLEMENT_PRESENCE required ${s_axi_mm}
-
-set s_axi_blk [ipx::add_address_block registers ${s_axi_mm}]
-set_property -dict { \
-	ACCESS "read-write" \
-	DESCRIPTION "Control and status registers" \
-	ENABLEMENT_PRESENCE required \
-	NAME "registers" \
-	RANGE 4096 \
-	USAGE "register" \
-	WIDTH 11 \
-	} ${s_axi_blk}
-
- # Save IP and close project
-ipx::check_integrity ${ip_core}
-ipx::save_core ${ip_core}
-close_project