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Commit d1d91dc4 authored by BRONES Romain's avatar BRONES Romain
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Moving component declaration in package

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hdl/comcellnode_ethernet.vhd
+ 2
− 188
View file @ d1d91dc4
library ieee;
use ieee.std_logic_1164.all;
use work.pkg_cc_ethernet.all;
entity comcellnode_ethernet is
port(
free_100_clk : in std_logic;
......@@ -104,194 +106,6 @@ architecture struct of comcellnode_ethernet is
ATTRIBUTE X_INTERFACE_INFO of sfp_tx_disable: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp TX_DISABLE";
ATTRIBUTE X_INTERFACE_INFO of sfp_tx_fault: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp TX_FAULT";
---------------------------
-- COMPONENT DECLARATION --
---------------------------
COMPONENT comcellnode_gtwizard
PORT (
gtwiz_userclk_tx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_srcclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_usrclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_usrclk2_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_active_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_srcclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_usrclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_usrclk2_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_active_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_clk_freerun_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_all_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_tx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_tx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_qpll0lock_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_cdr_stable_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_tx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_qpll0reset_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gthrxn_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gthrxp_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
loopback_in : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
qpll0clk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
qpll0refclk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
qpll1clk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
qpll1refclk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
rxgearboxslip_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
txdata_in : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
txheader_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
txsequence_in : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
gthtxn_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gthtxp_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtpowergood_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
rxdata_out : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
rxdatavalid_out : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
rxheader_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rxheadervalid_out : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
rxpmaresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
rxprgdivresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
rxstartofseq_out : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
txpmaresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
txprgdivresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
COMPONENT comcellnode_ethernet_core
PORT (
rx_core_clk_0 : IN STD_LOGIC;
rx_serdes_clk_0 : IN STD_LOGIC;
rx_serdes_reset_0 : IN STD_LOGIC;
rxgearboxslip_in_0 : OUT STD_LOGIC;
rxdatavalid_out_0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
rxheader_out_0 : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
rxheadervalid_out_0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
rx_serdes_data_out_0 : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
tx_serdes_data_in_0 : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
txheader_in_0 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
tx_core_clk_0 : IN STD_LOGIC;
ctl_gt_reset_all_0 : OUT STD_LOGIC;
ctl_gt_tx_reset_0 : OUT STD_LOGIC;
ctl_gt_rx_reset_0 : OUT STD_LOGIC;
s_axi_aclk_0 : IN STD_LOGIC;
s_axi_aresetn_0 : IN STD_LOGIC;
pm_tick_0 : IN STD_LOGIC;
s_axi_awaddr_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awvalid_0 : IN STD_LOGIC;
s_axi_awready_0 : OUT STD_LOGIC;
s_axi_wdata_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb_0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid_0 : IN STD_LOGIC;
s_axi_wready_0 : OUT STD_LOGIC;
s_axi_bresp_0 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid_0 : OUT STD_LOGIC;
s_axi_bready_0 : IN STD_LOGIC;
s_axi_araddr_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arvalid_0 : IN STD_LOGIC;
s_axi_arready_0 : OUT STD_LOGIC;
s_axi_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp_0 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid_0 : OUT STD_LOGIC;
s_axi_rready_0 : IN STD_LOGIC;
rx_reset_0 : IN STD_LOGIC;
rx_axis_tvalid_0 : OUT STD_LOGIC;
rx_axis_tdata_0 : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
rx_axis_tlast_0 : OUT STD_LOGIC;
rx_axis_tkeep_0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
rx_axis_tuser_0 : OUT STD_LOGIC;
stat_rx_framing_err_0 : OUT STD_LOGIC;
stat_rx_framing_err_valid_0 : OUT STD_LOGIC;
stat_rx_local_fault_0 : OUT STD_LOGIC;
stat_rx_block_lock_0 : OUT STD_LOGIC;
stat_rx_valid_ctrl_code_0 : OUT STD_LOGIC;
stat_rx_status_0 : OUT STD_LOGIC;
stat_rx_remote_fault_0 : OUT STD_LOGIC;
stat_rx_bad_fcs_0 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
stat_rx_stomped_fcs_0 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
stat_rx_truncated_0 : OUT STD_LOGIC;
stat_rx_internal_local_fault_0 : OUT STD_LOGIC;
stat_rx_received_local_fault_0 : OUT STD_LOGIC;
stat_rx_hi_ber_0 : OUT STD_LOGIC;
stat_rx_got_signal_os_0 : OUT STD_LOGIC;
stat_rx_test_pattern_mismatch_0 : OUT STD_LOGIC;
stat_rx_total_bytes_0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
stat_rx_total_packets_0 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
stat_rx_total_good_bytes_0 : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
stat_rx_total_good_packets_0 : OUT STD_LOGIC;
stat_rx_packet_bad_fcs_0 : OUT STD_LOGIC;
stat_rx_packet_64_bytes_0 : OUT STD_LOGIC;
stat_rx_packet_65_127_bytes_0 : OUT STD_LOGIC;
stat_rx_packet_128_255_bytes_0 : OUT STD_LOGIC;
stat_rx_packet_256_511_bytes_0 : OUT STD_LOGIC;
stat_rx_packet_512_1023_bytes_0 : OUT STD_LOGIC;
stat_rx_packet_1024_1518_bytes_0 : OUT STD_LOGIC;
stat_rx_packet_1519_1522_bytes_0 : OUT STD_LOGIC;
stat_rx_packet_1523_1548_bytes_0 : OUT STD_LOGIC;
stat_rx_packet_1549_2047_bytes_0 : OUT STD_LOGIC;
stat_rx_packet_2048_4095_bytes_0 : OUT STD_LOGIC;
stat_rx_packet_4096_8191_bytes_0 : OUT STD_LOGIC;
stat_rx_packet_8192_9215_bytes_0 : OUT STD_LOGIC;
stat_rx_packet_small_0 : OUT STD_LOGIC;
stat_rx_packet_large_0 : OUT STD_LOGIC;
stat_rx_unicast_0 : OUT STD_LOGIC;
stat_rx_multicast_0 : OUT STD_LOGIC;
stat_rx_broadcast_0 : OUT STD_LOGIC;
stat_rx_oversize_0 : OUT STD_LOGIC;
stat_rx_toolong_0 : OUT STD_LOGIC;
stat_rx_undersize_0 : OUT STD_LOGIC;
stat_rx_fragment_0 : OUT STD_LOGIC;
stat_rx_vlan_0 : OUT STD_LOGIC;
stat_rx_inrangeerr_0 : OUT STD_LOGIC;
stat_rx_jabber_0 : OUT STD_LOGIC;
stat_rx_bad_code_0 : OUT STD_LOGIC;
stat_rx_bad_sfd_0 : OUT STD_LOGIC;
stat_rx_bad_preamble_0 : OUT STD_LOGIC;
tx_reset_0 : IN STD_LOGIC;
tx_axis_tready_0 : OUT STD_LOGIC;
tx_axis_tvalid_0 : IN STD_LOGIC;
tx_axis_tdata_0 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
tx_axis_tlast_0 : IN STD_LOGIC;
tx_axis_tkeep_0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
tx_axis_tuser_0 : IN STD_LOGIC;
tx_unfout_0 : OUT STD_LOGIC;
tx_preamblein_0 : IN STD_LOGIC_VECTOR(55 DOWNTO 0);
rx_preambleout_0 : OUT STD_LOGIC_VECTOR(55 DOWNTO 0);
stat_tx_local_fault_0 : OUT STD_LOGIC;
stat_tx_total_bytes_0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
stat_tx_total_packets_0 : OUT STD_LOGIC;
stat_tx_total_good_bytes_0 : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
stat_tx_total_good_packets_0 : OUT STD_LOGIC;
stat_tx_bad_fcs_0 : OUT STD_LOGIC;
stat_tx_packet_64_bytes_0 : OUT STD_LOGIC;
stat_tx_packet_65_127_bytes_0 : OUT STD_LOGIC;
stat_tx_packet_128_255_bytes_0 : OUT STD_LOGIC;
stat_tx_packet_256_511_bytes_0 : OUT STD_LOGIC;
stat_tx_packet_512_1023_bytes_0 : OUT STD_LOGIC;
stat_tx_packet_1024_1518_bytes_0 : OUT STD_LOGIC;
stat_tx_packet_1519_1522_bytes_0 : OUT STD_LOGIC;
stat_tx_packet_1523_1548_bytes_0 : OUT STD_LOGIC;
stat_tx_packet_1549_2047_bytes_0 : OUT STD_LOGIC;
stat_tx_packet_2048_4095_bytes_0 : OUT STD_LOGIC;
stat_tx_packet_4096_8191_bytes_0 : OUT STD_LOGIC;
stat_tx_packet_8192_9215_bytes_0 : OUT STD_LOGIC;
stat_tx_packet_small_0 : OUT STD_LOGIC;
stat_tx_packet_large_0 : OUT STD_LOGIC;
stat_tx_unicast_0 : OUT STD_LOGIC;
stat_tx_multicast_0 : OUT STD_LOGIC;
stat_tx_broadcast_0 : OUT STD_LOGIC;
stat_tx_vlan_0 : OUT STD_LOGIC;
stat_tx_frame_error_0 : OUT STD_LOGIC;
ctl_tx_send_rfi_0 : IN STD_LOGIC;
ctl_tx_send_lfi_0 : IN STD_LOGIC;
ctl_tx_send_idle_0 : IN STD_LOGIC;
gt_loopback_out_0 : OUT STD_LOGIC;
gtwiz_reset_tx_done_0 : IN STD_LOGIC;
gtwiz_reset_rx_done_0 : IN STD_LOGIC;
user_reg0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
------------------------
-- SIGNAL DECLARATION --
------------------------
......
hdl/pkg_ccn_ethernet.vhd 0 → 100644
+ 192
− 0
View file @ d1d91dc4
library ieee;
use ieee.std_logic_1164.all;
package pkg_cc_ethernet is
--------------------------------------------
-- COMPONENT DECLARATION OF GENERATED IPS --
--------------------------------------------
COMPONENT comcellnode_gtwizard
PORT (
gtwiz_userclk_tx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_srcclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_usrclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_usrclk2_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_active_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_srcclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_usrclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_usrclk2_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_active_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_clk_freerun_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_all_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_tx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_tx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_qpll0lock_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_cdr_stable_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_tx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_qpll0reset_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gthrxn_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gthrxp_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
loopback_in : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
qpll0clk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
qpll0refclk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
qpll1clk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
qpll1refclk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
rxgearboxslip_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
txdata_in : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
txheader_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
txsequence_in : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
gthtxn_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gthtxp_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtpowergood_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
rxdata_out : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
rxdatavalid_out : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
rxheader_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rxheadervalid_out : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
rxpmaresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
rxprgdivresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
rxstartofseq_out : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
txpmaresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
txprgdivresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
COMPONENT comcellnode_ethernet_core
PORT (
rx_core_clk_0 : IN STD_LOGIC;
rx_serdes_clk_0 : IN STD_LOGIC;
rx_serdes_reset_0 : IN STD_LOGIC;
rxgearboxslip_in_0 : OUT STD_LOGIC;
rxdatavalid_out_0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
rxheader_out_0 : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
rxheadervalid_out_0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
rx_serdes_data_out_0 : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
tx_serdes_data_in_0 : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
txheader_in_0 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
tx_core_clk_0 : IN STD_LOGIC;
ctl_gt_reset_all_0 : OUT STD_LOGIC;
ctl_gt_tx_reset_0 : OUT STD_LOGIC;
ctl_gt_rx_reset_0 : OUT STD_LOGIC;
s_axi_aclk_0 : IN STD_LOGIC;
s_axi_aresetn_0 : IN STD_LOGIC;
pm_tick_0 : IN STD_LOGIC;
s_axi_awaddr_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awvalid_0 : IN STD_LOGIC;
s_axi_awready_0 : OUT STD_LOGIC;
s_axi_wdata_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb_0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid_0 : IN STD_LOGIC;
s_axi_wready_0 : OUT STD_LOGIC;
s_axi_bresp_0 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid_0 : OUT STD_LOGIC;
s_axi_bready_0 : IN STD_LOGIC;
s_axi_araddr_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arvalid_0 : IN STD_LOGIC;
s_axi_arready_0 : OUT STD_LOGIC;
s_axi_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp_0 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid_0 : OUT STD_LOGIC;
s_axi_rready_0 : IN STD_LOGIC;
rx_reset_0 : IN STD_LOGIC;
rx_axis_tvalid_0 : OUT STD_LOGIC;
rx_axis_tdata_0 : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
rx_axis_tlast_0 : OUT STD_LOGIC;
rx_axis_tkeep_0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
rx_axis_tuser_0 : OUT STD_LOGIC;
stat_rx_framing_err_0 : OUT STD_LOGIC;
stat_rx_framing_err_valid_0 : OUT STD_LOGIC;
stat_rx_local_fault_0 : OUT STD_LOGIC;
stat_rx_block_lock_0 : OUT STD_LOGIC;
stat_rx_valid_ctrl_code_0 : OUT STD_LOGIC;
stat_rx_status_0 : OUT STD_LOGIC;
stat_rx_remote_fault_0 : OUT STD_LOGIC;
stat_rx_bad_fcs_0 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
stat_rx_stomped_fcs_0 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
stat_rx_truncated_0 : OUT STD_LOGIC;
stat_rx_internal_local_fault_0 : OUT STD_LOGIC;
stat_rx_received_local_fault_0 : OUT STD_LOGIC;
stat_rx_hi_ber_0 : OUT STD_LOGIC;
stat_rx_got_signal_os_0 : OUT STD_LOGIC;
stat_rx_test_pattern_mismatch_0 : OUT STD_LOGIC;
stat_rx_total_bytes_0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
stat_rx_total_packets_0 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
stat_rx_total_good_bytes_0 : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
stat_rx_total_good_packets_0 : OUT STD_LOGIC;
stat_rx_packet_bad_fcs_0 : OUT STD_LOGIC;
stat_rx_packet_64_bytes_0 : OUT STD_LOGIC;
stat_rx_packet_65_127_bytes_0 : OUT STD_LOGIC;
stat_rx_packet_128_255_bytes_0 : OUT STD_LOGIC;
stat_rx_packet_256_511_bytes_0 : OUT STD_LOGIC;
stat_rx_packet_512_1023_bytes_0 : OUT STD_LOGIC;
stat_rx_packet_1024_1518_bytes_0 : OUT STD_LOGIC;
stat_rx_packet_1519_1522_bytes_0 : OUT STD_LOGIC;
stat_rx_packet_1523_1548_bytes_0 : OUT STD_LOGIC;
stat_rx_packet_1549_2047_bytes_0 : OUT STD_LOGIC;
stat_rx_packet_2048_4095_bytes_0 : OUT STD_LOGIC;
stat_rx_packet_4096_8191_bytes_0 : OUT STD_LOGIC;
stat_rx_packet_8192_9215_bytes_0 : OUT STD_LOGIC;
stat_rx_packet_small_0 : OUT STD_LOGIC;
stat_rx_packet_large_0 : OUT STD_LOGIC;
stat_rx_unicast_0 : OUT STD_LOGIC;
stat_rx_multicast_0 : OUT STD_LOGIC;
stat_rx_broadcast_0 : OUT STD_LOGIC;
stat_rx_oversize_0 : OUT STD_LOGIC;
stat_rx_toolong_0 : OUT STD_LOGIC;
stat_rx_undersize_0 : OUT STD_LOGIC;
stat_rx_fragment_0 : OUT STD_LOGIC;
stat_rx_vlan_0 : OUT STD_LOGIC;
stat_rx_inrangeerr_0 : OUT STD_LOGIC;
stat_rx_jabber_0 : OUT STD_LOGIC;
stat_rx_bad_code_0 : OUT STD_LOGIC;
stat_rx_bad_sfd_0 : OUT STD_LOGIC;
stat_rx_bad_preamble_0 : OUT STD_LOGIC;
tx_reset_0 : IN STD_LOGIC;
tx_axis_tready_0 : OUT STD_LOGIC;
tx_axis_tvalid_0 : IN STD_LOGIC;
tx_axis_tdata_0 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
tx_axis_tlast_0 : IN STD_LOGIC;
tx_axis_tkeep_0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
tx_axis_tuser_0 : IN STD_LOGIC;
tx_unfout_0 : OUT STD_LOGIC;
tx_preamblein_0 : IN STD_LOGIC_VECTOR(55 DOWNTO 0);
rx_preambleout_0 : OUT STD_LOGIC_VECTOR(55 DOWNTO 0);
stat_tx_local_fault_0 : OUT STD_LOGIC;
stat_tx_total_bytes_0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
stat_tx_total_packets_0 : OUT STD_LOGIC;
stat_tx_total_good_bytes_0 : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
stat_tx_total_good_packets_0 : OUT STD_LOGIC;
stat_tx_bad_fcs_0 : OUT STD_LOGIC;
stat_tx_packet_64_bytes_0 : OUT STD_LOGIC;
stat_tx_packet_65_127_bytes_0 : OUT STD_LOGIC;
stat_tx_packet_128_255_bytes_0 : OUT STD_LOGIC;
stat_tx_packet_256_511_bytes_0 : OUT STD_LOGIC;
stat_tx_packet_512_1023_bytes_0 : OUT STD_LOGIC;
stat_tx_packet_1024_1518_bytes_0 : OUT STD_LOGIC;
stat_tx_packet_1519_1522_bytes_0 : OUT STD_LOGIC;
stat_tx_packet_1523_1548_bytes_0 : OUT STD_LOGIC;
stat_tx_packet_1549_2047_bytes_0 : OUT STD_LOGIC;
stat_tx_packet_2048_4095_bytes_0 : OUT STD_LOGIC;
stat_tx_packet_4096_8191_bytes_0 : OUT STD_LOGIC;
stat_tx_packet_8192_9215_bytes_0 : OUT STD_LOGIC;
stat_tx_packet_small_0 : OUT STD_LOGIC;
stat_tx_packet_large_0 : OUT STD_LOGIC;
stat_tx_unicast_0 : OUT STD_LOGIC;
stat_tx_multicast_0 : OUT STD_LOGIC;
stat_tx_broadcast_0 : OUT STD_LOGIC;
stat_tx_vlan_0 : OUT STD_LOGIC;
stat_tx_frame_error_0 : OUT STD_LOGIC;
ctl_tx_send_rfi_0 : IN STD_LOGIC;
ctl_tx_send_lfi_0 : IN STD_LOGIC;
ctl_tx_send_idle_0 : IN STD_LOGIC;
gt_loopback_out_0 : OUT STD_LOGIC;
gtwiz_reset_tx_done_0 : IN STD_LOGIC;
gtwiz_reset_rx_done_0 : IN STD_LOGIC;
user_reg0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
end package pkg_cc_ethernet;
tcl/main.tcl
+ 1
− 0
View file @ d1d91dc4
......@@ -20,6 +20,7 @@ proc setSources {} {
lappend Vhdl ../hdl/comcellnode_ethernet.vhd
lappend Vhdl ../hdl/top_comcellnode_ethernet.vhd
lappend Vhdl ../hdl/pkg_comcellnode_ethernet_version.vhd
lappend Vhdl ../hdl/pkg_ccn_ethernet.vhd
lappend Verilog ../hdl/comcellnode_ethernet_reset_wrapper.v
......
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