TCL: Remove FPGA part set

Should be set by project script.

tcl/main.tcl

@@ -39,8 +39,6 @@ proc doOnCreate {} {
   addSources Vhdl
   addSources Verilog
 
-  set_property part ${::fwfwk::FpgaPart} [current_project]
-  set_property target_language VHDL [current_project]
   source generate_ethernet.tcl
 }