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Commit 6b17d06a authored by BRONES Romain's avatar BRONES Romain
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fix(rdl): specify hw access 

It was implicit before.
parent 7f8eec58
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rdl/xilinx_ethsubsyst.rdl
+ 186
− 186
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......@@ -9,17 +9,17 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="ctl gt reset all. 0 - Normal operation 1 - Reset the GT";
sw=rw;
sw=rw;hw=r;
} ctl_gt_reset_all[0:0];
field {
desc="ctl gt rx reset. 0 - Normal operation 1 - Reset the GT receiver";
sw=rw;
sw=rw;hw=r;
} ctl_gt_rx_reset[1:1];
field {
desc="ctl gt tx reset. 0 - Normal operation 1 - Reset the GT transmitter";
sw=rw;
sw=rw;hw=r;
} ctl_gt_tx_reset[2:2];
} GT_RESET_REG @ 0x0;
......@@ -28,22 +28,22 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="rx serdes reset. 0 - Normal operation 1 - Reset the Receiver serdes";
sw=rw;
sw=rw;hw=r;
} rx_serdes_reset[0:0];
field {
desc="tx serdes reset. 0 - Normal operation 1 - Reset the transmitter serdes";
sw=rw;
sw=rw;hw=r;
} tx_serdes_reset[29:29];
field {
desc="rx reset. 0 - Normal operation 1 - Reset the receiver ";
sw=rw;
sw=rw;hw=r;
} rx_reset[30:30];
field {
desc="tx_reset. 0 - Normal operation 1 - Reset the transmitter";
sw=rw;
sw=rw;hw=r;
} tx_reset[31:31];
} RESET_REG @ 0x0004;
......@@ -52,12 +52,12 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="tick reg mode sel. 1 - tick_reg is used to read the statistics counters.";
sw=rw;
sw=rw;hw=r;
} tick_reg_mode_sel[30:30];
field {
desc="ctl local loopback. 0 - Normal operation 1 - places the transceiver into the PMA loopback state. ";
sw=rw;
sw=rw;hw=r;
} ctl_local_loopback[31:31];
} MODE_REG @ 0x0008;
......@@ -66,67 +66,67 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="ctl tx enable. 0 - only IDLEs are transmitted by the core. 1 - Enables the transmission of data. ";
sw=rw;
sw=rw;hw=r;
} ctl_tx_enable[0:0];
field {
desc="ctl tx fcs ins enable. 0 - the core does not add FCS to packet. 1 - the core calculates and adds the FCS to the packet. ";
sw=rw;
sw=rw;hw=r;
} ctl_tx_fcs_ins_enable[1:1];
field {
desc="ctl tx ignore fcs. 0 - A packet with bad FCS is being transmitted, it is not binned as good. 1 - A packet with bad FCS is binned as good.";
sw=rw;
sw=rw;hw=r;
} ctl_tx_ignore_fcs[2:2];
field {
desc="ctl tx send lfi. 0 - Normal operation 1 - Transmit Local Fault Indication (LFI) code word. Takes precedence over Remote Fault Indication (RFI).";
sw=rw;
sw=rw;hw=r;
} ctl_tx_send_lfi[3:3];
field {
desc="ctl tx send rfi. 0 - Normal operation 1 - the TX path transmits only RFI code words.";
sw=rw;
sw=rw;hw=r;
} ctl_tx_send_rfi[4:4];
field {
desc="ctl tx send idle. 0 - Normal operation 1 - The TX path only transmits Idle code words.";
sw=rw;
sw=rw;hw=r;
} ctl_tx_send_idle[5:5];
field {
desc="ctl tx ipg value. This signal can be optionally present. The ctl_tx_ipg_value defines the target average minimum Inter Packet Gap (IPG, in bytes) inserted between AXI4-Stream packets. Valid values are 8 to 12.";
sw=rw;
sw=rw;hw=r;
} ctl_tx_ipg_value[13:10];
field {
desc="ctl tx test pattern. 0 - Normal operation 1 - Test pattern generation enable for the TX core. A value of 1 enables test mode.";
sw=rw;
sw=rw;hw=r;
} ctl_tx_test_pattern[14:14];
field {
desc="ctl tx test pattern enable. 0 - Normal operation 1 - Test pattern generation enable for the TX core.";
sw=rw;
sw=rw;hw=r;
} ctl_tx_test_pattern_enable[15:15];
field {
desc="ctl tx test pattern select. Corresponds to MDIO register 3.34 through to 3.37 as defined in Clause 45.";
sw=rw;
sw=rw;hw=r;
} ctl_tx_test_pattern_select[16:16];
field {
desc="ctl tx data pattern select. Corresponds to MDIO register 3.34 through to 3.37 as defined in Clause 45.";
sw=rw;
sw=rw;hw=r;
} ctl_tx_data_pattern_select[17:17];
field {
desc="ctl_tx_custom_preamble_enable. 0 - Normal operation 1 - When it is set, the use of tx_preamblein as a custom preamble instead of inserting a standard preamble. ";
sw=rw;
sw=rw;hw=r;
} ctl_tx_custom_preamble_enable[18:18];
field {
desc="ctl tx prbs31 test pattern enable. Corresponds to MDIO register 3.34 through to 3.37 as defined in Clause 45.";
sw=rw;
sw=rw;hw=r;
} ctl_tx_prbs31_test_pattern_enable[23:23];
} CONFIGURATION_TX_REG1 @ 0x000C;
......@@ -135,62 +135,62 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="ctl rx enable. 0 - The RX completes the reception of the current packet (if any), it stops receiving packets by keeping the PCS from decoding incoming data. 1 - Normal operation ";
sw=rw;
sw=rw;hw=r;
} ctl_rx_enable[0:0];
field {
desc="ctl rx delete fcs. 0 - the core does not remove the FCS of the incoming packet. 1 - the core deletes the FCS to the received packet. ";
sw=rw;
sw=rw;hw=r;
} ctl_rx_delete_fcs[1:1];
field {
desc="ctl rx ignore fcs. 0 - A packet received with an FCS error is sent with the rx_axis_tuser pin asserted during the last transfer (rx_axis_tlast sampled 1). 1 - The core does not flag an FCS error at the AXI4-Stream interface.";
sw=rw;
sw=rw;hw=r;
} ctl_rx_ignore_fcs[2:2];
field {
desc="ctl rx process lfi. 0 - the RX core ignores LF control codes coming in from the transceiver. 1 - the RX core expects and processes LF control codes coming in from the transceiver.";
sw=rw;
sw=rw;hw=r;
} ctl_rx_process_lfi[3:3];
field {
desc="ctl rx check sfd. 0 - Normal operation 1 - this input causes the MAC to check the Start of Frame Delimiter of the received frame.";
sw=rw;
sw=rw;hw=r;
} ctl_rx_check_sfd[4:4];
field {
desc="ctl rx check preamble. 0 - Normal operation 1 - this input causes the MAC to check the preamble of the received frame.";
sw=rw;
sw=rw;hw=r;
} ctl_rx_check_preamble[5:5];
field {
desc="ctl rx force resync. 0 - Normal operation 1 - forces the reset operation.";
sw=rw;
sw=rw;hw=r;
} ctl_rx_force_resync[6:6];
field {
desc="Test pattern checking enable for the RX core. 0 - Normal operation 1 - Enables test mode.";
sw=rw;
sw=rw;hw=r;
} ctl_rx_test_pattern[7:7];
field {
desc="Test pattern enable for the RX core. 0 - Normal operation 1 - Enables test mode. ";
sw=rw;
sw=rw;hw=r;
} ctl_rx_test_pattern_enable[8:8];
field {
desc="Data pattern select for RX core. Corresponds to MDIO register 3.34 through to 3.37 as defined in Clause 45.";
sw=rw;
sw=rw;hw=r;
} ctl_rx_data_pattern_select[9:9];
field {
desc="ctl_rx_custom_preamble_enable. 0 - Normal operation 1 - This signal causes the side band of a packet presented on the AXI4-Stream to be the preamble as it appears on the line. ";
sw=rw;
sw=rw;hw=r;
} ctl_rx_custom_preamble_enable[11:11];
field {
desc="ctl rx prbs31 test pattern enable. Corresponds to MDIO register 3.34 through to 3.37 as defined in Clause 45.";
sw=rw;
sw=rw;hw=r;
} ctl_rx_prbs31_test_pattern_enable[12:12];
} CONFIGURATION_RX_REG1 @ 0x0014;
......@@ -199,12 +199,12 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="ctl rx min packet len. Any packet shorter than this value is considered to be undersized. If a packet has a size less than this value, the rx_axis_tuser signal is asserted during the rx_axis_tlast asserted cycle.";
sw=rw;
sw=rw;hw=r;
} ctl_rx_min_packet_len[7:0];
field {
desc="ctl rx max packet len. Any packet longer than this value is considered to be oversized.";
sw=rw;
sw=rw;hw=r;
} ctl_rx_max_packet_len[30:16];
} CONFIGURATION_RX_MTU @ 0x0018;
......@@ -213,7 +213,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="tick reg.";
sw=w;
sw=r;hw=rw;
} tick_reg[0:0];
} TICK_REG @ 0x0020;
......@@ -222,17 +222,17 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="major revision.";
sw=r;
sw=r;hw=rw;
} major_rev[7:0];
field {
desc="minor revision.";
sw=r;
sw=r;hw=rw;
} minor_rev[15:8];
field {
desc="patch revision.";
sw=r;
sw=r;hw=rw;
} patch_rev[31:24];
} CONFIGURATION_REVISION_REG @ 0x0024;
......@@ -241,7 +241,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="ctl tx test pattern seed a. Corresponds to MDIO registers 3.34 through to 3.37 as defined in Clause 45.";
sw=rw;
sw=rw;hw=r;
} ctl_tx_test_pattern_seed_a_reg0[31:0];
} CONFIGURATION_TX_TEST_PAT_SEED_A_LSB @ 0x0028;
......@@ -250,7 +250,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="ctl tx test pattern seed a. Corresponds to MDIO registers 3.34 through to 3.37 as defined in Clause 45.";
sw=rw;
sw=rw;hw=r;
} ctl_tx_test_pattern_seed_a_reg1[25:0];
} CONFIGURATION_TX_TEST_PAT_SEED_A_MSB @ 0x002C;
......@@ -259,7 +259,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="ctl tx test pattern seed b. Corresponds to MDIO registers 3.38 through to 3.41 as defined in Clause 45.";
sw=rw;
sw=rw;hw=r;
} ctl_tx_test_pattern_seed_b_reg0[31:0];
} CONFIGURATION_TX_TEST_PAT_SEED_B_LSB @ 0x0030;
......@@ -268,7 +268,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="ctl tx test pattern seed b. Corresponds to MDIO registers 3.38 through to 3.41 as defined in Clause 45.";
sw=rw;
sw=rw;hw=r;
} ctl_tx_test_pattern_seed_b_reg1[25:0];
} CONFIGURATION_TX_TEST_PAT_SEED_B_MSB @ 0x0034;
......@@ -277,7 +277,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="user register0. User-defined signal from the AXI4-Reg map user_reg0 register.";
sw=rw;
sw=rw;hw=r;
} user_reg0[31:0];
} USER_REG_0 @ 0x0134;
......@@ -286,7 +286,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="axi ctl core mode switch. 0 - Normal operation 1 - Enables the mode switch line rate from 10G and 25G and vice versa.";
sw=rw;
sw=rw;hw=r;
} axi_ctl_core_mode_switch[0:0];
} SWITCH_CORE_SPEED_REG @ 0x0138;
......@@ -295,22 +295,22 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx local fault. 0 - Normal operation 1 - Indicates the receive decoder state machine is in the TX_INIT state. This output is level sensitive. ";
sw=r;
sw=r;hw=rw;
} stat_tx_local_fault[0:0];
field {
desc="stat tx gmii fifo ovf 1h r out. TX FIFO overflow.";
sw=r;
sw=r;hw=rw;
} stat_tx_gmii_fifo_ovf_1h_r_out[1:1];
field {
desc="stat tx gmii fifo unf 1h r out. TX FIFO underflow.";
sw=r;
sw=r;hw=rw;
} stat_tx_gmii_fifo_unf_1h_r_out[2:2];
field {
desc="stat tx bad parity. Increment on any clock cycle where the user-generated parity is calculated as incorrect by the Tx parity checking logic.";
sw=r;
sw=r;hw=rw;
} stat_tx_bad_parity[7:7];
} STAT_TX_STATUS_REG1 @ 0x0400;
......@@ -319,42 +319,42 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx hi ber. High Bit Error Rate Indicator. 1 - the BER is too high as defined by IEEE Std. 802.3. Corresponds to MDIO register bit 3.32.1 as defined in Clause 49.2.14.";
sw=r;
sw=r;hw=rw;
} stat_rx_hi_ber[4:4];
field {
desc="stat rx remote fault. 0 - Remote fault condition does not exist. 1 - It indicates a remote fault condition was detected. ";
sw=r;
sw=r;hw=rw;
} stat_rx_remote_fault[5:5];
field {
desc="stat rx local fault. 1 - indicates the receive decoder state machine is in the RX_INIT state.";
sw=r;
sw=r;hw=rw;
} stat_rx_local_fault[6:6];
field {
desc="stat rx internal local fault. 1 - when an internal local fault is generated due to test pattern generation or high bit error rate. ";
sw=r;
sw=r;hw=rw;
} stat_rx_internal_local_fault[7:7];
field {
desc="stat rx received local fault. 0 - Normal operation 1 - when enough local fault words are received from the link partner to trigger a fault condition as specified by the IEEE fault state machine. Remains High as long as the fault condition persists.";
sw=r;
sw=r;hw=rw;
} stat_rx_received_local_fault[8:8];
field {
desc="stat rx bad preamble. 0 - Indicates that an invalid preamble was not received. 1 - Indicates that an invalid preamble was received.";
sw=r;
sw=r;hw=rw;
} stat_rx_bad_preamble[9:9];
field {
desc="stat rx bad sfd. Increment bad SFD. 0 - Indicates that an invalid SFD was not received. 1 - Indicates that an invalid SFD was received.";
sw=r;
sw=r;hw=rw;
} stat_rx_bad_sfd[10:10];
field {
desc="stat rx got signal os. Signal OS indication. 1 - It indicates that a signal OS word was received.";
sw=r;
sw=r;hw=rw;
} stat_rx_got_signal_os[11:11];
} STAT_RX_STATUS_REG1 @ 0x0404;
......@@ -363,22 +363,22 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx fifo error. Transmit clock compensation FIFO error indicator. 0 - Normal operation 1 - Indicates the clock compensation FIFO under or overflowed.";
sw=r;
sw=r;hw=rw;
} stat_tx_fifo_error[0:0];
field {
desc="stat tx ptp fifo read error. Transmit PTP FIFO read error. 0 - Normal operation 1 - Indicates that an error occurred during the PTP Tag read.";
sw=r;
sw=r;hw=rw;
} stat_tx_ptp_fifo_read_error[4:4];
field {
desc="stat tx ptp fifo write error. Transmit PTP FIFO write error. 0 - Normal operation 1 - Indicates that an error occurred during the PTP Tag write. ";
sw=r;
sw=r;hw=rw;
} stat_tx_ptp_fifo_write_error[5:5];
field {
desc="stat rx fifo error. Receive clock compensation FIFO error indicator. 0 - Normal operation 1 - Indicates the clock compensation FIFO under or overflowed.";
sw=r;
sw=r;hw=rw;
} stat_rx_fifo_error[16:16];
} STAT_STATUS_REG1 @ 0x0408;
......@@ -387,7 +387,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx block lock Block lock status. 1 - Indicates that block lock is achieved as defined in Clause 49.2.14 and MDIO register 3.32.0";
sw=r;
sw=r;hw=rw;
} stat_rx_block_lock[0:0];
} STAT_RX_BLOCK_LOCK_REG @ 0x040C;
......@@ -396,7 +396,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx valid ctrl code. 1 - Indicates that a PCS block with a valid control code was received.";
sw=r;
sw=r;hw=rw;
} stat_rx_valid_ctrl_code[0:0];
} STAT_RX_VALID_CTRL_CODE @ 0x0494;
......@@ -405,12 +405,12 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat core speed. 0 - Standalone 25G 1 - Standalone 10G";
sw=r;
sw=r;hw=rw;
} stat_core_speed[0:0];
field {
desc="runtime switchable. 0 - Runtime Switchable 25G 1 - Runtime Switchable 10G";
sw=r;
sw=r;hw=rw;
} runtime_switchable[1:1];
} STAT_CORE_SPEED_REG @ 0x0498;
......@@ -419,12 +419,12 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="GT TX reset Done";
sw=r;
sw=r;hw=rw;
} gtwiz_reset_tx_done[0:0];
field {
desc="GT TX reset Done";
sw=r;
sw=r;hw=rw;
} gtwiz_reset_rx_done[1:1];
} STAT_GT_WIZ_REG @ 0x04A0;
......@@ -433,7 +433,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat cycle reg0. Contains a count of the number of RX core clock cycles between TICK_REG writes.";
sw=r;
sw=r;hw=rw;
} stat_cycle_reg0[31:0];
} STATUS_CYCLE_COUNT_LSB @ 0x0500;
......@@ -442,7 +442,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat cycle reg1. Contains a count of the number of RX core clock cycles between TICK_REG writes.";
sw=r;
sw=r;hw=rw;
} stat_cycle_reg1[15:0];
} STATUS_CYCLE_COUNT_MSB @ 0x0504;
......@@ -451,7 +451,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx framing err reg0. RX sync header bits framing error. Each PCS Lane has a four-bit bus that indicates how many sync header errors were received for that PCS Lane. The value of the bus is only valid when the corresponding stat_rx_framing_err_valid is a 1. The values on these buses can be updated at any time and are intended to be used as increment values for sync header error counters.";
sw=r;
sw=r;hw=rw;
} stat_rx_framing_err_reg0[31:0];
} STAT_RX_FRAMING_ERR_LSB @ 0x0648;
......@@ -460,7 +460,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx framing err reg1. RX sync header bits framing error. Each PCS Lane has a four-bit bus that indicates how many sync header errors were received for that PCS Lane. The value of the bus is only valid when the corresponding stat_rx_framing_err_valid is a 1. The values on these buses can be updated at any time and are intended to be used as increment values for sync header error counters.";
sw=r;
sw=r;hw=rw;
} stat_rx_framing_err_reg1[15:0];
} STAT_RX_FRAMING_ERR_MSB @ 0x064C;
......@@ -469,7 +469,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx bad code reg0. Increment for 64B/66B code violations. This signal indicates that the RX PCS receive state machine is in the RX_E state as specified by the IEEE Std 802.3-2015. ";
sw=r;
sw=r;hw=rw;
} stat_rx_bad_code_reg0[31:0];
} STAT_RX_BAD_CODE_LSB @ 0x0660;
......@@ -478,7 +478,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx bad code reg1. Increment for 64B/66B code violations. This signal indicates that the RX PCS receive state machine is in the RX_E state as specified by the IEEE Std 802.3-2015.";
sw=r;
sw=r;hw=rw;
} stat_rx_bad_code_reg1[15:0];
} STAT_RX_BAD_CODE_MSB @ 0x0664;
......@@ -487,7 +487,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx frame error reg0. Increment for packets with tx_axis_tuser set to indicate an End of Packet(EOP) abort.";
sw=r;
sw=r;hw=rw;
} stat_tx_frame_error_reg0[31:0];
} STAT_TX_FRAME_ERROR_LSB @ 0x06A0;
......@@ -496,7 +496,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx frame error reg1. Increment for packets with tx_axis_tuser set to indicate an End of Packet(EOP) abort.";
sw=r;
sw=r;hw=rw;
} stat_tx_frame_error_reg1[15:0];
} STAT_TX_FRAME_ERROR_MSB @ 0x06A4;
......@@ -505,7 +505,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx total packets reg0. Increment for the total number of packets transmitted.";
sw=r;
sw=r;hw=rw;
} stat_tx_total_packets_reg0[31:0];
} STAT_TX_TOTAL_PACKETS_LSB @ 0x0700;
......@@ -514,7 +514,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx total packets reg1. Increment for the total number of packets transmitted.";
sw=r;
sw=r;hw=rw;
} stat_tx_total_packets_reg1[15:0];
} STAT_TX_TOTAL_PACKETS_MSB @ 0x0704;
......@@ -523,7 +523,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx total good packets reg0. Increment for the total number of good packets transmitted.";
sw=r;
sw=r;hw=rw;
} stat_tx_total_good_packets_reg0[31:0];
} STAT_TX_TOTAL_GOOD_PACKETS_LSB @ 0x0708;
......@@ -532,7 +532,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx total good packets reg1. Increment for the total number of good packets transmitted.";
sw=r;
sw=r;hw=rw;
} stat_tx_total_good_packets_reg1[15:0];
} STAT_TX_TOTAL_GOOD_PACKETS_MSB @ 0x070C;
......@@ -541,7 +541,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx total bytes reg0. Increment for the total number of bytes transmitted.";
sw=r;
sw=r;hw=rw;
} stat_tx_total_bytes_reg0[31:0];
} STAT_TX_TOTAL_BYTES_LSB @ 0x0710;
......@@ -550,7 +550,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx total bytes reg1. Increment for the total number of bytes transmitted.";
sw=r;
sw=r;hw=rw;
} stat_tx_total_bytes_reg1[15:0];
} STAT_TX_TOTAL_BYTES_MSB @ 0x0714;
......@@ -559,7 +559,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx total good bytes reg0. Increment for the total number of good bytes transmitted. This value is only non-zero when a packet is transmitted completely and contains no errors.";
sw=r;
sw=r;hw=rw;
} stat_tx_total_good_bytes_reg0[31:0];
} STAT_TX_TOTAL_GOOD_BYTES_LSB @ 0x0718;
......@@ -568,7 +568,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx total good bytes reg1. Increment for the total number of good bytes transmitted. This value is only non-zero when a packet is transmitted completely and contains no errors.";
sw=r;
sw=r;hw=rw;
} stat_tx_total_good_bytes_reg1[15:0];
} STAT_TX_TOTAL_GOOD_BYTES_MSB @ 0x071C;
......@@ -577,7 +577,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx packet 64 bytes reg0. Increment for good and bad packets transmitted that contain 64 bytes.";
sw=r;
sw=r;hw=rw;
} stat_tx_packet_64_bytes_reg0[31:0];
} STAT_TX_PACKET_64_BYTES_LSB @ 0x0720;
......@@ -586,7 +586,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx packet 64 bytes reg1. Increment for good and bad packets transmitted that contain 64 bytes.";
sw=r;
sw=r;hw=rw;
} stat_tx_packet_64_bytes_reg1[15:0];
} STAT_TX_PACKET_64_BYTES_MSB @ 0x0724;
......@@ -595,7 +595,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx packet 65 - 127 bytes reg0. Increment for good and bad packets transmitted that contain 65 to 127 bytes.";
sw=r;
sw=r;hw=rw;
} stat_tx_packet_65_127_bytes_reg0[31:0];
} STAT_TX_PACKET_65_127_BYTES_LSB @ 0x0728;
......@@ -604,7 +604,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx packet 65-127 bytes reg1. Increment for good and bad packets transmitted that contain 65 to 127 bytes.";
sw=r;
sw=r;hw=rw;
} stat_tx_packet_65_127_bytes_reg1[15:0];
} STAT_TX_PACKET_65_127_BYTES_MSB @ 0x072C;
......@@ -613,7 +613,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx packet 128-255 bytes reg0. Increment for good and bad packets transmitted that contain 128 to 255 bytes.";
sw=r;
sw=r;hw=rw;
} stat_tx_packet_128_255_bytes_reg0[31:0];
} STAT_TX_PACKET_128_255_BYTES_LSB @ 0x0730;
......@@ -622,7 +622,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx packet 128-255 bytes reg1. Increment for good and bad packets transmitted that contain 128 to 255 bytes.";
sw=r;
sw=r;hw=rw;
} stat_tx_packet_128_255_bytes_reg1[15:0];
} STAT_TX_PACKET_128_255_BYTES_MSB @ 0x0734;
......@@ -631,7 +631,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx packet 256-511 bytes reg0. Increment for good and bad packets transmitted that contain 256 to 511 bytes.";
sw=r;
sw=r;hw=rw;
} stat_tx_packet_256_511_bytes_reg0[31:0];
} STAT_TX_PACKET_256_511_BYTES_LSB @ 0x0738;
......@@ -640,7 +640,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx packet 256-511 bytes reg1. Increment for good and bad packets transmitted that contain 256 to 511 bytes.";
sw=r;
sw=r;hw=rw;
} stat_tx_packet_256_511_bytes_reg1[15:0];
} STAT_TX_PACKET_256_511_BYTES_MSB @ 0x073C;
......@@ -649,7 +649,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx packet 512-1023 bytes reg0. Increment for good and bad packets transmitted that contain 512 to 1,023 bytes.";
sw=r;
sw=r;hw=rw;
} stat_tx_packet_512_1023_bytes_reg0[31:0];
} STAT_TX_PACKET_512_1023_BYTES_LSB @ 0x0740;
......@@ -658,7 +658,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx packet 512-1023 bytes reg1. Increment for good and bad packets transmitted that contain 512 to 1,023 bytes.";
sw=r;
sw=r;hw=rw;
} stat_tx_packet_512_1023_bytes_reg1[15:0];
} STAT_TX_PACKET_512_1023_BYTES_MSB @ 0x0744;
......@@ -667,7 +667,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx packet 1024-1518 bytes reg0. Increment for good and bad packets transmitted that contain 1,024 to 1,518 bytes.";
sw=r;
sw=r;hw=rw;
} stat_tx_packet_1024_1518_bytes_reg0[31:0];
} STAT_TX_PACKET_1024_1518_BYTES_LSB @ 0x0748;
......@@ -676,7 +676,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx packet 1024-1518 bytes reg1. Increment for good and bad packets transmitted that contain 1,024 to 1,518 bytes.";
sw=r;
sw=r;hw=rw;
} stat_tx_packet_1024_1518_bytes_reg1[15:0];
} STAT_TX_PACKET_1024_1518_BYTES_MSB @ 0x074C;
......@@ -685,7 +685,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx packet 1519-1522 bytes reg0. Increment for good and bad packets transmitted that contain 1,519 to 1,522 bytes.";
sw=r;
sw=r;hw=rw;
} stat_tx_packet_1519_1522_bytes_reg0[31:0];
} STAT_TX_PACKET_1519_1522_BYTES_LSB @ 0x0750;
......@@ -694,7 +694,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx packet 1519-1522 bytes reg1. Increment for good and bad packets transmitted that contain 1,519 to 1,522 bytes.";
sw=r;
sw=r;hw=rw;
} stat_tx_packet_1519_1522_bytes__reg1[15:0];
} STAT_TX_PACKET_1519_1522_BYTES_MSB @ 0x0754;
......@@ -703,7 +703,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx packet 1523-1548 bytes reg0. Increment for good and bad packets transmitted that contain 1,523 to 1,548 bytes.";
sw=r;
sw=r;hw=rw;
} stat_tx_packet_1523_1548_bytes_reg0[31:0];
} STAT_TX_PACKET_1523_1548_BYTES_LSB @ 0x0758;
......@@ -712,7 +712,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx packet 1523-1548 bytes reg1. Increment for good and bad packets transmitted that contain 1,523 to 1,548 bytes.";
sw=r;
sw=r;hw=rw;
} stat_tx_packet_1523_1548_bytes_reg1[15:0];
} STAT_TX_PACKET_1523_1548_BYTES_MSB @ 0x075C;
......@@ -721,7 +721,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx packet 1549-2047 bytes reg0. Increment for good and bad packets transmitted that contain 1,549 to 2,047 bytes.";
sw=r;
sw=r;hw=rw;
} stat_tx_packet_1549_2047_bytes_reg0[31:0];
} STAT_TX_PACKET_1549_2047_BYTES_LSB @ 0x0760;
......@@ -730,7 +730,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx packet 1549-2047 bytes reg1. Increment for good and bad packets transmitted that contain 1,549 to 2,047 bytes.";
sw=r;
sw=r;hw=rw;
} stat_tx_packet_1549_2047_bytes_reg1[15:0];
} STAT_TX_PACKET_1549_2047_BYTES_MSB @ 0x0764;
......@@ -739,7 +739,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx packet 2048-4095 bytes reg0. Increment for good and bad packets transmitted that contain 2,048 to 4,095 bytes.";
sw=r;
sw=r;hw=rw;
} stat_tx_packet_2048_4095_bytes_reg0[31:0];
} STAT_TX_PACKET_2048_4095_BYTES_LSB @ 0x0768;
......@@ -748,7 +748,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx packet 2048-4095 bytes reg1. Increment for good and bad packets transmitted that contain 2,048 to 4,095 bytes.";
sw=r;
sw=r;hw=rw;
} stat_tx_packet_2048_4095_bytes_reg1[15:0];
} STAT_TX_PACKET_2048_4095_BYTES_MSB @ 0x076C;
......@@ -757,7 +757,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx packet 4096-8191 bytes reg0. Increment for good and bad packets transmitted that contain 4,096 to 8,191 bytes.";
sw=r;
sw=r;hw=rw;
} stat_tx_packet_4096_8191_bytes_reg0[31:0];
} STAT_TX_PACKET_4096_8191_BYTES_LSB @ 0x0770;
......@@ -766,7 +766,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx packet 4096-8191 bytes reg1. Increment for good and bad packets transmitted that contain 4,096 to 8,191 bytes.";
sw=r;
sw=r;hw=rw;
} stat_tx_packet_4096_8191_bytes_reg1[15:0];
} STAT_TX_PACKET_4096_8191_BYTES_MSB @ 0x0774;
......@@ -775,7 +775,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx packet 8192-9215 bytes reg0. Increment for good and bad packets transmitted that contain 8,192 to 9,215 bytes.";
sw=r;
sw=r;hw=rw;
} stat_tx_packet_8192_9215_bytes_reg0[31:0];
} STAT_TX_PACKET_8192_9215_BYTES_LSB @ 0x0778;
......@@ -784,7 +784,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx packet 8192-9215 bytes reg1. Increment for good and bad packets transmitted that contain 8,192 to 9,215 bytes.";
sw=r;
sw=r;hw=rw;
} stat_tx_packet_8192_9215_bytes_reg1[15:0];
} STAT_TX_PACKET_8192_9215_BYTES_MSB @ 0x077C;
......@@ -793,7 +793,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx packet large reg0. Increment for all packets that are more than 9,215 bytes long.";
sw=r;
sw=r;hw=rw;
} stat_tx_packet_large_reg0[31:0];
} STAT_TX_PACKET_LARGE_LSB @ 0x0780;
......@@ -802,7 +802,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx packet large reg1. Increment for all packets that are more than 9,215 bytes long.";
sw=r;
sw=r;hw=rw;
} stat_tx_packet_large_reg1[15:0];
} STAT_TX_PACKET_LARGE_MSB @ 0x0784;
......@@ -811,7 +811,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx packet small reg0. Increment for all packets that are less than 64 bytes long.";
sw=r;
sw=r;hw=rw;
} stat_tx_packet_small_reg0[31:0];
} STAT_TX_PACKET_SMALL_LSB @ 0x0788;
......@@ -820,7 +820,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx packet small reg1. Increment for all packets that are less than 64 bytes long.";
sw=r;
sw=r;hw=rw;
} stat_tx_packet_small_reg1[15:0];
} STAT_TX_PACKET_SMALL_MSB @ 0x078C;
......@@ -829,7 +829,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx bad fcs reg0. Increment for packets greater than 64 bytes that have FCS errors.";
sw=r;
sw=r;hw=rw;
} stat_tx_bad_fcs_reg0[31:0];
} STAT_TX_BAD_FCS_LSB @ 0x07B8;
......@@ -838,7 +838,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx bad fcs reg1. Increment for packets greater than 64 bytes that have FCS errors.";
sw=r;
sw=r;hw=rw;
} stat_tx_bad_fcs_reg1[15:0];
} STAT_TX_BAD_FCS_MSB @ 0x07BC;
......@@ -847,7 +847,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx unicast reg0. Increment for good unicast packets.";
sw=r;
sw=r;hw=rw;
} stat_tx_unicast_reg0[31:0];
} STAT_TX_UNICAST_LSB @ 0x07D0;
......@@ -856,7 +856,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx unicast reg1. Increment for good unicast packets.";
sw=r;
sw=r;hw=rw;
} stat_tx_unicast_reg1[15:0];
} STAT_TX_UNICAST_MSB @ 0x07D4;
......@@ -865,7 +865,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx multicast reg0. Increment for good multicast packets.";
sw=r;
sw=r;hw=rw;
} stat_tx_multicast_reg0[31:0];
} STAT_TX_MULTICAST_LSB @ 0x07D8;
......@@ -874,7 +874,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx multicast reg1. Increment for good multicast packets.";
sw=r;
sw=r;hw=rw;
} stat_tx_multicast_reg1[15:0];
} STAT_TX_MULTICAST_MSB @ 0x07DC;
......@@ -883,7 +883,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx broadcast reg0. Increment for good broadcast packets.";
sw=r;
sw=r;hw=rw;
} stat_tx_broadcast_reg0[31:0];
} STAT_TX_BROADCAST_LSB @ 0x07E0;
......@@ -892,7 +892,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx broadcast reg1. Increment for good broadcast packets.";
sw=r;
sw=r;hw=rw;
} stat_tx_broadcast_reg1[15:0];
} STAT_TX_BROADCAST_MSB @ 0x07E4;
......@@ -901,7 +901,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx vlan reg0. Increment for good 802.1Q tagged VLAN packets.";
sw=r;
sw=r;hw=rw;
} stat_tx_vlan_reg0[31:0];
} STAT_TX_VLAN_LSB @ 0x07E8;
......@@ -910,7 +910,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat tx vlan reg1. Increment for good 802.1Q tagged VLAN packets.";
sw=r;
sw=r;hw=rw;
} stat_tx_vlan_reg1[15:0];
} STAT_TX_VLAN_MSB @ 0x07EC;
......@@ -919,7 +919,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx total packets reg0. Increment for the total number of packets received.";
sw=r;
sw=r;hw=rw;
} stat_rx_total_packets_reg0[31:0];
} STAT_RX_TOTAL_PACKETS_LSB @ 0x0808;
......@@ -928,7 +928,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx total packets reg1. Increment for the total number of packets received.";
sw=r;
sw=r;hw=rw;
} stat_rx_total_packets_reg1[15:0];
} STAT_RX_TOTAL_PACKETS_MSB @ 0x080C;
......@@ -937,7 +937,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx total good packets reg0. Increment for the total number of good bytes received. This value is only non-zero when a packet is received completely and contains no errors.";
sw=r;
sw=r;hw=rw;
} stat_rx_total_good_packets_reg0[31:0];
} STAT_RX_TOTAL_GOOD_PACKETS_LSB @ 0x0810;
......@@ -946,7 +946,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx total good packets reg1. Increment for the total number of good bytes received. This value is only non-zero when a packet is received completely and contains no errors.";
sw=r;
sw=r;hw=rw;
} stat_rx_total_good_packets_reg1[15:0];
} STAT_RX_TOTAL_GOOD_PACKETS_MSB @ 0x0814;
......@@ -955,7 +955,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx total bytes reg0. Increment for the total number of bytes received.";
sw=r;
sw=r;hw=rw;
} stat_rx_total_bytes_reg0[31:0];
} STAT_RX_TOTAL_BYTES_LSB @ 0x0818;
......@@ -964,7 +964,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx total bytes reg1. Increment for the total number of bytes received.";
sw=r;
sw=r;hw=rw;
} stat_rx_total_bytes_reg1[15:0];
} STAT_RX_TOTAL_BYTES_MSB @ 0x081C;
......@@ -973,7 +973,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx total good bytes reg0. Increment for the total number of good bytes received. This value is only non-zero when a packet is received completely and contains no errors.";
sw=r;
sw=r;hw=rw;
} stat_rx_total_good_bytes_reg0[31:0];
} STAT_RX_TOTAL_GOOD_BYTES_LSB @ 0x0820;
......@@ -982,7 +982,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx total good bytes reg1. Increment for the total number of good bytes received. This value is only non-zero when a packet is received completely and contains no errors.";
sw=r;
sw=r;hw=rw;
} stat_rx_total_good_bytes_reg1[15:0];
} STAT_RX_TOTAL_GOOD_BYTES_MSB @ 0x0824;
......@@ -991,7 +991,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx packet 64 bytes reg0. Increment for good and bad packets received that contain 64 bytes.";
sw=r;
sw=r;hw=rw;
} stat_rx_packet_64_bytes_reg0[31:0];
} STAT_RX_PACKET_64_BYTES_LSB @ 0x0828;
......@@ -1000,7 +1000,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx packet 64 bytes reg1. Increment for good and bad packets received that contain 64 bytes.";
sw=r;
sw=r;hw=rw;
} stat_rx_packet_64_bytes_reg1[15:0];
} STAT_RX_PACKET_64_BYTES_MSB @ 0x082C;
......@@ -1009,7 +1009,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx packet 65-127 bytes reg0. Increment for good and bad packets received that contain 65 to 127 bytes.";
sw=r;
sw=r;hw=rw;
} stat_rx_packet_65_127_bytes_reg0[31:0];
} STAT_RX_PACKET_65_127_BYTES_LSB @ 0x0830;
......@@ -1018,7 +1018,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx packet 65-127 bytes reg1. Increment for good and bad packets received that contain 65 to 127 bytes.";
sw=r;
sw=r;hw=rw;
} stat_rx_packet_65_127_bytes_reg1[15:0];
} STAT_RX_PACKET_65_127_BYTES_MSB @ 0x0834;
......@@ -1027,7 +1027,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx packet 128-255 bytes reg0. Increment for good and bad packets received that contain 128 to 255 bytes. ";
sw=r;
sw=r;hw=rw;
} stat_rx_packet_128_255_bytes_reg0[31:0];
} STAT_RX_PACKET_128_255_BYTES_LSB @ 0x0838;
......@@ -1036,7 +1036,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx packet 128-255 bytes reg1. Increment for good and bad packets received that contain 128 to 255 bytes.";
sw=r;
sw=r;hw=rw;
} stat_rx_packet_128_255_bytes_reg1[15:0];
} STAT_RX_PACKET_128_255_BYTES_MSB @ 0x083C;
......@@ -1045,7 +1045,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx packet 256-511 bytes reg0. Increment for good and bad packets received that contain 256 to 511 bytes.";
sw=r;
sw=r;hw=rw;
} stat_rx_packet_256_511_bytes_reg0[31:0];
} STAT_RX_PACKET_256_511_BYTES_LSB @ 0x0840;
......@@ -1054,7 +1054,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx packet 256-511 bytes reg1. Increment for good and bad packets received that contain 256 to 511 bytes.";
sw=r;
sw=r;hw=rw;
} stat_rx_packet_256_511_bytes_reg1[15:0];
} STAT_RX_PACKET_256_511_BYTES_MSB @ 0x0844;
......@@ -1063,7 +1063,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx packet 512-1023 bytes reg0. Increment for good and bad packets received that contain 512 to 1,023 bytes.";
sw=r;
sw=r;hw=rw;
} stat_rx_packet_512_1023_bytes_reg0[31:0];
} STAT_RX_PACKET_512_1023_BYTES_LSB @ 0x0848;
......@@ -1072,7 +1072,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx packet 512-1023 bytes reg1. Increment for good and bad packets received that contain 512 to 1,023 bytes.";
sw=r;
sw=r;hw=rw;
} stat_rx_packet_512_1023_bytes_reg1[15:0];
} STAT_RX_PACKET_512_1023_BYTES_MSB @ 0x084C;
......@@ -1081,7 +1081,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx packet 1024-1518 bytes reg0. Increment for good and bad packets received that contain 1,024 to 1,518 bytes.";
sw=r;
sw=r;hw=rw;
} stat_rx_packet_1024_1518_bytes_reg0[31:0];
} STAT_RX_PACKET_1024_1518_BYTES_LSB @ 0x0850;
......@@ -1090,7 +1090,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx packet 1024-1518 bytes reg1. Increment for good and bad packets received that contain 1,024 to 1,518 bytes.";
sw=r;
sw=r;hw=rw;
} stat_rx_packet_1024_1518_bytes_reg1[15:0];
} STAT_RX_PACKET_1024_1518_BYTES_MSB @ 0x0854;
......@@ -1099,7 +1099,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx packet 1519-1522 bytes reg0. Increment for good and bad packets received that contain 1519 to 1522 bytes.";
sw=r;
sw=r;hw=rw;
} stat_rx_packet_1519_1522_bytes_reg0[31:0];
} STAT_RX_PACKET_1519_1522_BYTES_LSB @ 0x0858;
......@@ -1108,7 +1108,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx packet 1519-1522 bytes reg1. Increment for good and bad packets received that contain 1519 to 1522 bytes.";
sw=r;
sw=r;hw=rw;
} stat_rx_packet_1519_1522_bytes_reg1[15:0];
} STAT_RX_PACKET_1519_1522_BYTES_MSB @ 0x085C;
......@@ -1117,7 +1117,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx packet 1523-1548 bytes reg0. Increment for good and bad packets received that contain 1,523 to 1,548 bytes.";
sw=r;
sw=r;hw=rw;
} stat_rx_packet_1523_1548_bytes_reg0[31:0];
} STAT_RX_PACKET_1523_1548_BYTES_LSB @ 0x0860;
......@@ -1126,7 +1126,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx packet 1523-1548 bytes reg1. Increment for good and bad packets received that contain 1,523 to 1,548 bytes.";
sw=r;
sw=r;hw=rw;
} stat_rx_packet_1523_1548_bytes_reg1[15:0];
} STAT_RX_PACKET_1523_1548_BYTES_MSB @ 0x0864;
......@@ -1135,7 +1135,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx packet 1549-2047 bytes reg0. Increment for good and bad packets received that contain 1,549 to 2,047 bytes.";
sw=r;
sw=r;hw=rw;
} stat_rx_packet_1549_2047_bytes_reg0[31:0];
} STAT_RX_PACKET_1549_2047_BYTES_LSB @ 0x0868;
......@@ -1144,7 +1144,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx packet 1549-2047 bytes reg1. Increment for good and bad packets received that contain 1,549 to 2,047 bytes.";
sw=r;
sw=r;hw=rw;
} stat_rx_packet_1549_2047_bytes_reg1[15:0];
} STAT_RX_PACKET_1549_2047_BYTES_MSB @ 0x086C;
......@@ -1153,7 +1153,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx packet 2048-4095 bytes reg0. Increment for good and bad packets received that contain 2,048 to 4,095 bytes.";
sw=r;
sw=r;hw=rw;
} stat_rx_packet_2048_4095_bytes_reg0[31:0];
} STAT_RX_PACKET_2048_4095_BYTES_LSB @ 0x0870;
......@@ -1162,7 +1162,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx packet 2048-4095 bytes reg1. Increment for good and bad packets received that contain 2,048 to 4,095 bytes.";
sw=r;
sw=r;hw=rw;
} stat_rx_packet_2048_4095_bytes_reg1[15:0];
} STAT_RX_PACKET_2048_4095_BYTES_MSB @ 0x0874;
......@@ -1171,7 +1171,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx packet 4096-8191 bytes reg0. Increment for good and bad packets received that contain 4,096 to 8,191 bytes.";
sw=r;
sw=r;hw=rw;
} stat_rx_packet_4096_8191_bytes_reg0[31:0];
} STAT_RX_PACKET_4096_8191_BYTES_LSB @ 0x0878;
......@@ -1180,7 +1180,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx packet 4096-8191 bytes reg1. Increment for good and bad packets received that contain 4,096 to 8,191 bytes.";
sw=r;
sw=r;hw=rw;
} stat_rx_packet_4096_8191_bytes_reg1[15:0];
} STAT_RX_PACKET_4096_8191_BYTES_MSB @ 0x087C;
......@@ -1189,7 +1189,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx packet 8192-9215 bytes reg0. Increment for good and bad packets received that contain 8,192 to 9,215 bytes.";
sw=r;
sw=r;hw=rw;
} stat_rx_packet_8192_9215_bytes_reg0[31:0];
} STAT_RX_PACKET_8192_9215_BYTES_LSB @ 0x0880;
......@@ -1198,7 +1198,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx packet 8192-9215 bytes reg1. Increment for good and bad packets received that contain 8,192 to 9,215 bytes.";
sw=r;
sw=r;hw=rw;
} stat_rx_packet_8192_9215_bytes_reg1[15:0];
} STAT_RX_PACKET_8192_9215_BYTES_MSB @ 0x0884;
......@@ -1207,7 +1207,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx packet large reg0. Increment for all packets that are more than 9,215 bytes long.";
sw=r;
sw=r;hw=rw;
} stat_rx_packet_large_reg0[31:0];
} STAT_RX_PACKET_LARGE_LSB @ 0x0888;
......@@ -1216,7 +1216,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx packet large reg1. Increment for all packets that are more than 9,215 bytes long.";
sw=r;
sw=r;hw=rw;
} stat_rx_packet_large_reg1[15:0];
} STAT_RX_PACKET_LARGE_MSB @ 0x088C;
......@@ -1225,7 +1225,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx packet small reg0. Increment for all packets that are less than 64 bytes long. Packets that are less than four bytes are dropped.";
sw=r;
sw=r;hw=rw;
} stat_rx_packet_small_reg0[31:0];
} STAT_RX_PACKET_SMALL_LSB @ 0x0890;
......@@ -1234,7 +1234,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx packet small reg1. Increment for all packets that are less than 64 bytes long. Packets that are less than four bytes are dropped.";
sw=r;
sw=r;hw=rw;
} stat_rx_packet_small_reg1[15:0];
} STAT_RX_PACKET_SMALL_MSB @ 0x0894;
......@@ -1243,7 +1243,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx undersize reg0. Increment for packets shorter than ctl_rx_min_packet_len with good FCS.";
sw=r;
sw=r;hw=rw;
} stat_rx_undersize_reg0[31:0];
} STAT_RX_UNDERSIZE_LSB @ 0x0898;
......@@ -1252,7 +1252,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx undersize reg1. Increment for packets shorter than ctl_rx_min_packet_len with good FCS.";
sw=r;
sw=r;hw=rw;
} stat_rx_undersize_reg1[15:0];
} STAT_RX_UNDERSIZE_MSB @ 0x089C;
......@@ -1261,7 +1261,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx fragment reg0. Increment for packets shorter than ctl_rx_min_packet_len with bad FCS.";
sw=r;
sw=r;hw=rw;
} stat_rx_fragment_reg0[31:0];
} STAT_RX_FRAGMENT_LSB @ 0x8A0;
......@@ -1270,7 +1270,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx fragment reg1. Increment for packets shorter than ctl_rx_min_packet_len with bad FCS.";
sw=r;
sw=r;hw=rw;
} stat_rx_fragment_reg1[15:0];
} STAT_RX_FRAGMENT_MSB @ 0x8A4;
......@@ -1279,7 +1279,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx oversize reg0. Increment for packets longer than ctl_rx_max_packet_len with good FCS.";
sw=r;
sw=r;hw=rw;
} stat_rx_oversize_reg0[31:0];
} STAT_RX_OVERSIZE_LSB @ 0x08A8;
......@@ -1288,7 +1288,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx oversize reg1. Increment for packets longer than ctl_rx_max_packet_len with good FCS.";
sw=r;
sw=r;hw=rw;
} stat_rx_oversize_reg1[15:0];
} STAT_RX_OVERSIZE_MSB @ 0x08AC;
......@@ -1297,7 +1297,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx toolong reg0. Increment for packets longer than ctl_rx_max_packet_len with good and bad FCS.";
sw=r;
sw=r;hw=rw;
} stat_rx_toolong_reg0[31:0];
} STAT_RX_TOOLONG_LSB @ 0x08B0;
......@@ -1306,7 +1306,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx toolong reg1. Increment for packets longer than ctl_rx_max_packet_len with good and bad FCS.";
sw=r;
sw=r;hw=rw;
} stat_rx_toolong_reg1[15:0];
} STAT_RX_TOOLONG_MSB @ 0x08B4;
......@@ -1315,7 +1315,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx jabber reg0. Increment for packets longer than ctl_rx_max_packet_len with bad FCS.";
sw=r;
sw=r;hw=rw;
} stat_rx_jabber_reg0[31:0];
} STAT_RX_JABBER_LSB @ 0x08B8;
......@@ -1324,7 +1324,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx jabber reg1. Increment for packets longer than ctl_rx_max_packet_len with bad FCS.";
sw=r;
sw=r;hw=rw;
} stat_rx_jabber_reg1[15:0];
} STAT_RX_JABBER_MSB @ 0x08BC;
......@@ -1333,7 +1333,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx bad fcs reg0. Bad FCS indicator. The value on this bus indicates packets received with a bad FCS, but not a stomped FCS during a cycle. This output is pulsed for one clock cycle to indicate an error condition.";
sw=r;
sw=r;hw=rw;
} stat_rx_bad_fcs_reg0[31:0];
} STAT_RX_BAD_FCS_LSB @ 0x08C0;
......@@ -1342,7 +1342,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx bad fcs reg1. Bad FCS indicator. The value on this bus indicates packets received with a bad FCS, but not a stomped FCS during a cycle. This output is pulsed for one clock cycle to indicate an error condition.";
sw=r;
sw=r;hw=rw;
} stat_rx_bad_fcs_reg1[15:0];
} STAT_RX_BAD_FCS_MSB @ 0x08C4;
......@@ -1351,7 +1351,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx packet bad fcs reg0. Increment for packets between 64 and ctl_rx_max_packet_len bytes that have Frame Check Sequence (FCS) errors.";
sw=r;
sw=r;hw=rw;
} stat_rx_packet_bad_fcs_reg0[31:0];
} STAT_RX_PACKET_BAD_FCS_LSB @ 0x08C8;
......@@ -1360,7 +1360,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx packet bad fcs reg1. Increment for packets between 64 and ctl_rx_max_packet_len bytes that have Frame Check Sequence (FCS) errors.";
sw=r;
sw=r;hw=rw;
} stat_rx_packet_bad_fcs_reg1[15:0];
} STAT_RX_PACKET_BAD_FCS_MSB @ 0x08CC;
......@@ -1369,7 +1369,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx stomped fcs reg0. Stomped FCS indicator. The value on this bus indicates the packets were received with a stomped FCS. A stomped FCS is defined as the bitwise inverse of the expected good FCS. This output is pulsed for one clock cycle to indicate the stomped condition.";
sw=r;
sw=r;hw=rw;
} stat_rx_stomped_fcs_reg0[31:0];
} STAT_RX_STOMPED_FCS_LSB @ 0x08D0;
......@@ -1378,7 +1378,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx stomped fcs reg1. Stomped FCS indicator. The value on this bus indicates the packets were received with a stomped FCS. A stomped FCS is defined as the bitwise inverse of the expected good FCS. This output is pulsed for one clock cycle to indicate the stomped condition.";
sw=r;
sw=r;hw=rw;
} stat_rx_stomped_fcs_reg1[15:0];
} STAT_RX_STOMPED_FCS_MSB @ 0x08D4;
......@@ -1387,7 +1387,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx unicast reg0. Increment for good unicast packets.";
sw=r;
sw=r;hw=rw;
} stat_rx_unicast_reg0[31:0];
} STAT_RX_UNICAST_LSB @ 0x08D8;
......@@ -1396,7 +1396,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx unicast reg1. Increment for good unicast packets.";
sw=r;
sw=r;hw=rw;
} stat_rx_unicast_reg1[15:0];
} STAT_RX_UNICAST_MSB @ 0x08DC;
......@@ -1405,7 +1405,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx multicast reg0. Increment for good multicast packets.";
sw=r;
sw=r;hw=rw;
} stat_rx_multicast_reg0[31:0];
} STAT_RX_MULTICAST_LSB @ 0x08E0;
......@@ -1414,7 +1414,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx multicast reg1. Increment for good multicast packets.";
sw=r;
sw=r;hw=rw;
} stat_rx_multicast_reg1[15:0];
} STAT_RX_MULTICAST_MSB @ 0x08E4;
......@@ -1423,7 +1423,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx broadcast reg0. Increment for good broadcast packets.";
sw=r;
sw=r;hw=rw;
} stat_rx_broadcast_reg0[31:0];
} STAT_RX_BROADCAST_LSB @ 0x08E8;
......@@ -1432,7 +1432,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx broadcast reg1. Increment for good broadcast packets.";
sw=r;
sw=r;hw=rw;
} stat_rx_broadcast_reg1[15:0];
} STAT_RX_BROADCAST_MSB @ 0x08EC;
......@@ -1441,7 +1441,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx vlan reg0. Increment for good 802.1Q tagged VLAN packets.";
sw=r;
sw=r;hw=rw;
} stat_rx_vlan_reg0[31:0];
} STAT_RX_VLAN_LSB @ 0x08F0;
......@@ -1450,7 +1450,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx vlan reg1. Increment for good 802.1Q tagged VLAN packets.";
sw=r;
sw=r;hw=rw;
} stat_rx_vlan_reg1[15:0];
} STAT_RX_VLAN_MSB @ 0x08F4;
......@@ -1459,7 +1459,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx inrangeerr reg0. Increment for packets with Length field error but with good FCS.";
sw=r;
sw=r;hw=rw;
} stat_rx_inrangeerr_reg0[31:0];
} STAT_RX_INRANGEERR_LSB @ 0x0908;
......@@ -1468,7 +1468,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx inrangeerr reg1. Increment for packets with Length field error but with good FCS.";
sw=r;
sw=r;hw=rw;
} stat_rx_inrangeerr_reg1[15:0];
} STAT_RX_INRANGEERR_MSB @ 0x090C;
......@@ -1477,7 +1477,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx test pattern mismatch reg0. Test pattern mismatch increment. A non-zero value in any cycle indicates how many mismatches occurred for the test pattern in the RX core. This output is only active when ctl_rx_test_pattern is set to a 1. This output can be used to generate MDIO register as defined in Clause 45. This output is pulsed for one clock cycle.";
sw=r;
sw=r;hw=rw;
} stat_rx_test_pattern_mismatch_reg0[31:0];
} STAT_RX_TEST_PATTERN_MISMATCH_LSB @ 0x0918;
......@@ -1486,7 +1486,7 @@ addrmap xilinx_ethsubsyst {
reg {
field {
desc="stat rx test pattern mismatch reg1. Test pattern mismatch increment. A non-zero value in any cycle indicates how many mismatches occurred for the test pattern in the RX core. This output is only active when ctl_rx_test_pattern is set to a 1. This output can be used to generate MDIO register as defined in Clause 45. This output is pulsed for one clock cycle.";
sw=r;
sw=r;hw=rw;
} stat_rx_test_pattern_mismatch_reg1[15:0];
} STAT_RX_TEST_PATTERN_MISMATCH_MSB @ 0x091C;
......
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