feat:Bring GT powergood signal to top level interface

* This is used for QPLL reset when several core are present

hdl/top_ccn_ethernet.vhd

@@ -25,6 +25,7 @@ entity top_ccn_ethernet is
         qpll0refclk_in              : in std_logic;
         qpll0lock_in                : in std_logic;
         qpll0reset_out              : out std_logic;
+        gt_powergood                : out std_logic;
 
         -- AXI-MM Status and Config
         s_axi_m2s                   : in  t_ccn_ethernet_m2s;
@@ -64,6 +65,7 @@ architecture rtl of top_ccn_ethernet is
     signal addrmap_i           : t_addrmap_ccn_ethernet_in;
     signal addrmap_o           : t_addrmap_ccn_ethernet_out;
     signal areset              : std_logic;
+    signal s_gt_powergood      : std_logic;
 
 begin
 
@@ -84,6 +86,9 @@ begin
 
     addrmap_i.version.data.data  <= C_VERSION;
 
+    addrmap_i.gt_status.powergood.data(0) <= s_gt_powergood;
+    gt_powergood                          <= s_gt_powergood;
+
     --------------
     -- ETHERNET --
     --------------
@@ -123,7 +128,7 @@ begin
         -- Status
         tx_clk_active                      => addrmap_i.gt_status.tx_clk_active.data(0),
         rx_clk_active                      => addrmap_i.gt_status.rx_clk_active.data(0),
-        gt_powergood                       => addrmap_i.gt_status.powergood.data(0),
+        gt_powergood                       => s_gt_powergood,
         cdr_stable                         => addrmap_i.gt_status.cdr_stable.data(0),
         rx_los                             => addrmap_i.gt_status.sfp_rx_los.data(0),
         mod_abs                            => addrmap_i.gt_status.sfp_mod_abs.data(0),