feat:Add pps input for ethernet statistics

* PPS input is connected to pm_tick of the Eth block
* Filter for rising edge capture.

hdl/ccn_ethernet.vhd

@@ -40,6 +40,7 @@ entity ccn_ethernet is
         sfp_tx_fault                       : in std_logic;
 
         -- Status
+        pm_tick                            : in std_logic;
         tx_clk_active                      : out std_logic;
         rx_clk_active                      : out std_logic;
         gt_powergood                       : out std_logic;
@@ -331,6 +332,9 @@ begin
             tx_unfout_0                      => txunderflow,
             user_reg0_0                      => userreg,
 
+            -- Stat latch tick
+            pm_tick_0                        => pm_tick,
+
             -- Unused
             tx_preamblein_0                  => (others => '0'),
             rx_preambleout_0                 => open,
@@ -339,7 +343,6 @@ begin
             ctl_tx_send_idle_0               => '0',
 
             -- Unused (stat)
-            pm_tick_0                        => '0',
             stat_rx_framing_err_0            => open,
             stat_rx_framing_err_valid_0      => open,
             stat_rx_local_fault_0            => open,

hdl/top_ccn_ethernet.vhd

@@ -27,6 +27,9 @@ entity top_ccn_ethernet is
         qpll0reset_out              : out std_logic;
         gt_powergood                : out std_logic;
 
+        -- PPS input
+        pps                         : in std_logic;
+
         -- AXI-MM Status and Config
         s_axi_m2s                   : in  t_ccn_ethernet_m2s;
         s_axi_s2m                   : out t_ccn_ethernet_s2m;
@@ -67,10 +70,24 @@ architecture rtl of top_ccn_ethernet is
     signal areset              : std_logic;
     signal s_gt_powergood      : std_logic;
 
+    signal pps_r               : std_logic;
+    signal pps_pulse           : std_logic;
+
 begin
 
     areset <= not aresetn;
 
+    -- Pulse filter
+    rfilter_p:process(aclk, areset)
+    begin
+        if areset = '1' then
+            pps_r   <= '0';
+        elsif rising_edge(aclk) then
+            pps_r <= pps;
+        end if;
+    end process;
+    pps_pulse <= pps and (not pps_r);
+
     ----------------------
     -- AXI-MM INTERFACE --
     ----------------------
@@ -126,6 +143,7 @@ begin
         sfp_tx_fault                       => sfp_tx_fault,
 
         -- Status
+        pm_tick                            => pps_pulse,
         tx_clk_active                      => addrmap_i.gt_status.tx_clk_active.data(0),
         rx_clk_active                      => addrmap_i.gt_status.rx_clk_active.data(0),
         gt_powergood                       => s_gt_powergood,