Add CDC between AXIMM and logic

* This is cleaner, but they were false path anyway (slow configuration)

hdl/top_ccn_ethernet.vhd

@@ -10,6 +10,9 @@ library ccn_eth_lib;
 use ccn_eth_lib.pkg_ccn_ethernet.all;
 use ccn_eth_lib.pkg_ccn_ethernet_version.all;
 
+library xpm;
+use xpm.vcomponents.all;
+
 entity top_ccn_ethernet is
     generic(
         G_IPNUM                            : natural :=  0
@@ -70,10 +73,18 @@ architecture rtl of top_ccn_ethernet is
     signal areset              : std_logic;
     signal s_gt_powergood      : std_logic;
 
+    signal ccn_clk             : std_logic;
+    signal tx_clk_active       : std_logic;
+    signal rx_clk_active       : std_logic;
+    signal gt_rx_out_clk       : std_logic;
+    signal rx_rst              : std_logic;
+
 begin
 
     areset <= not aresetn;
 
+    axis_clk <= ccn_clk;
+
     ----------------------
     -- AXI-MM INTERFACE --
     ----------------------
@@ -92,6 +103,34 @@ begin
     addrmap_i.gt_status.powergood.data(0) <= s_gt_powergood;
     gt_powergood                          <= s_gt_powergood;
 
+    ---------
+    -- CDC --
+    ---------
+    inst_cdc_tx_clk_active: xpm_cdc_single
+    port map(
+        src_in      => tx_clk_active,
+        src_clk     => ccn_clk,
+        dest_clk    => aclk,
+        dest_out    => addrmap_i.gt_status.tx_clk_active.data(0)
+    );
+
+    inst_cdc_rx_clk_active: xpm_cdc_single
+    port map(
+        src_in      => rx_clk_active,
+        src_clk     => gt_rx_out_clk,
+        dest_clk    => aclk,
+        dest_out    => addrmap_i.gt_status.rx_clk_active.data(0)
+    );
+
+    inst_cdc_rx_rst: xpm_cdc_single
+    port map(
+        src_in      => addrmap_o.gt_control.rst_rx.data(0),
+        src_clk     => aclk,
+        dest_clk    => ccn_clk,
+        dest_out    => rx_rst
+    );
+
+
     --------------
     -- ETHERNET --
     --------------
@@ -100,7 +139,7 @@ begin
     port map(
         free_100_clk                       => free_100_clk,
         axi_clk                            => aclk,
-        axis_clk                           => axis_clk,
+        axis_clk                           => ccn_clk,
         rst_n                              => aresetn,
 
         qpll0clk_in                        => qpll0clk_in,
@@ -113,9 +152,9 @@ begin
         tx_data_rst                        => addrmap_o.gt_control.rst_tx_data.data(0),
         rx_data_rst                        => addrmap_o.gt_control.rst_rx_data.data(0),
         tx_rst                             => addrmap_o.gt_control.rst_tx.data(0),
-        rx_rst                             => addrmap_o.gt_control.rst_rx.data(0),
+        rx_rst                             => rx_rst,
         gt_loopback                        => addrmap_o.gt_control.loopback.data,
-        gt_rx_out_clk                      => open,
+        gt_rx_out_clk                      => gt_rx_out_clk,
         gt_tx_out_clk                      => open,
 
         -- SFP signals
@@ -130,8 +169,8 @@ begin
 
         -- Status
         pm_tick                            => pps,
-        tx_clk_active                      => addrmap_i.gt_status.tx_clk_active.data(0),
-        rx_clk_active                      => addrmap_i.gt_status.rx_clk_active.data(0),
+        tx_clk_active                      => tx_clk_active,
+        rx_clk_active                      => rx_clk_active,
         gt_powergood                       => s_gt_powergood,
         cdr_stable                         => addrmap_i.gt_status.cdr_stable.data(0),
         rx_los                             => addrmap_i.gt_status.sfp_rx_los.data(0),