fix: Corrections on reset engine

hdl/ccn_ethernet_reset.vhd

@@ -2,6 +2,9 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
+library xpm;
+use xpm.vcomponents.all;
+
 entity ccn_ethernet_reset is
 port(
 
@@ -33,11 +36,11 @@ port(
     core_tx_rst_i   : in std_logic;
     core_tx_rst_o   : out std_logic;
     core_rx_rst_i   : in std_logic; -- registered on txusrclk
-    core_rx_rst_o   : out std_logic;
+    core_rx_rst_o   : out std_logic
 );
 end entity;
 
-architecture rtl of ccn_ethernet_reset
+architecture rtl of ccn_ethernet_reset is
 
     signal r_ctl_all_rst     : std_logic;
     signal r_ctl_rx_rst      : std_logic;
@@ -53,7 +56,7 @@ architecture rtl of ccn_ethernet_reset
     signal r_core_rx_rst     : std_logic;
     signal s_core_rx_rst     : std_logic;
 
-    signal s_gt_serdes_rx_rst: std_logic
+    signal s_gt_serdes_rx_rst: std_logic;
 
 begin
 
@@ -64,7 +67,7 @@ begin
     -- registers ctl rst
     process(s_axi_aclk)
     begin
-        if rising_edge(s_axi_aclk)
+        if rising_edge(s_axi_aclk) then
             r_ctl_all_rst    <= ctl_all_rst_i;
             r_ctl_tx_rst     <= ctl_tx_rst_i;
             r_ctl_rx_rst     <= ctl_rx_rst_i;
@@ -75,21 +78,21 @@ begin
     inst_cdc_freeclk_all : xpm_cdc_sync_rst
     port map (
         dest_clk        => freeclk,
-        dest_rst_out    => s_ctl_all_rst,
+        dest_rst        => s_ctl_all_rst,
         src_rst         => r_ctl_all_rst
     );
 
     inst_cdc_freeclk_rx : xpm_cdc_sync_rst
     port map (
         dest_clk        => freeclk,
-        dest_rst_out    => s_ctl_rx_rst,
+        dest_rst        => s_ctl_rx_rst,
         src_rst         => r_ctl_rx_rst
     );
 
     inst_cdc_freeclk_tx : xpm_cdc_sync_rst
     port map (
         dest_clk        => freeclk,
-        dest_rst_out    => s_ctl_tx_rst,
+        dest_rst        => s_ctl_tx_rst,
         src_rst         => r_ctl_tx_rst
     );
 
@@ -105,15 +108,15 @@ begin
     -- CDC to GT txusrclk
     inst_cdc_txusrclk_rx : xpm_cdc_sync_rst
     port map (
-        dest_clk        => gt_tx_usrclk
-        dest_rst_out    => s_gt_tx_rst,
+        dest_clk        => gt_tx_usrclk,
+        dest_rst        => s_gt_tx_rst,
         src_rst         => gt_tx_rst_i
     );
 
     inst_cdc_rxusrclk_rx : xpm_cdc_sync_rst
     port map (
-        dest_clk        => gt_tx_usrclk
-        dest_rst_out    => s_gt_rx_rst,
+        dest_clk        => gt_tx_usrclk,
+        dest_rst        => s_gt_rx_rst,
         src_rst         => gt_rx_rst_i
     );
 
@@ -124,7 +127,7 @@ begin
     process(gt_tx_usrclk)
     begin
         if rising_edge(gt_tx_usrclk) then
-            r_core_nrst <= (not s_gt_rx_rst) or core_rx_rst_i;
+            r_core_rx_rst <= (not s_gt_rx_rst) or core_rx_rst_i;
         end if;
     end process;
 
@@ -137,24 +140,26 @@ begin
     inst_cdc_rxusrclk : xpm_cdc_sync_rst
     port map (
         dest_clk        => gt_rx_usrclk,
-        dest_rst_out    => s_gt_serdes_rx_rst,
+        dest_rst        => s_gt_serdes_rx_rst,
         src_rst         => r_core_rx_rst
     );
 
     -- output on GT rxusrclk
-    gt_serdes_rx_rst_o  <=  s_gt_serdes_rx_rst
+    gt_serdes_rx_rst_o  <=  s_gt_serdes_rx_rst;
 
     ----------
     -- CORE --
     ----------
 
     -- CDC to rx core clk
-    inst_cdc_rxusrclk : xpm_cdc_sync_rst
+    inst_cdc_rxcoreclk : xpm_cdc_sync_rst
     port map (
         dest_clk        => core_rx_clk,
-        dest_rst_out    => s_core_rx_rst,
+        dest_rst        => s_core_rx_rst,
         src_rst         => r_core_rx_rst
     );
 
     -- ouput on rx core clk
     core_rx_rst_o       <= s_core_rx_rst;
+
+end architecture rtl;