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Commit 4b57735c authored by BRONES Romain's avatar BRONES Romain
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wip: add generate+generic based instanciation

parent 7d495c5c
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......@@ -5,6 +5,9 @@ library ccn_eth_lib;
use ccn_eth_lib.pkg_ccn_ethernet.all;
entity ccn_ethernet is
generic(
G_IPNUM : natural := 0
);
port(
free_100_clk : in std_logic;
axi_clk : in std_logic;
......@@ -142,6 +145,7 @@ architecture struct of ccn_ethernet is
signal txunderflow : std_logic;
signal userreg : std_logic_vector(31 downto 0);
begin
gt_rx_out_clk <= rxusrclk2;
......@@ -156,7 +160,39 @@ begin
axis_clk <= main_clk;
inst_gtwizard:ccn_gtwizard
inst_reset_helper: entity ccn_eth_lib.ccn_ethernet_reset_wrapper
port map(
sys_reset => rst,
dclk => free_100_clk,
s_axi_aclk => axi_clk,
ctl_gt_reset_all => gt_rst_all,
ctl_gt_tx_reset => gt_rst_tx,
ctl_gt_rx_reset => gt_rst_rx,
gtwiz_reset_tx_datapath => tx_data_rst,
gtwiz_reset_rx_datapath => rx_data_rst,
gt_txusrclk2 => main_clk,
gt_rxusrclk2 => rxusrclk2,
rx_core_clk => main_clk,
gt_tx_reset_in => gtwiz_tx_rst_done,
gt_rx_reset_in => gtwiz_rx_rst_done,
tx_core_reset_in => tx_rst,
rx_core_reset_in => rx_rst,
tx_core_reset_out => tx_rst_core,
rx_core_reset_out => rx_rst_core,
rx_serdes_reset_out => rx_serdes_rst,
usr_tx_reset => open,
usr_rx_reset => open,
gtwiz_reset_all => gtwiz_reset_all,
gtwiz_reset_tx_datapath_out => gtwiz_rst_tx_datapath,
gtwiz_reset_rx_datapath_out => gtwiz_rst_rx_datapath
);
-- GENRATE "mux" TO SELECT GOOD IP
-- Very dumb, but I did not find anything smarter...
G0:if G_IPNUM=0 generate
inst_gtwizard:ccn_gtwizard_0
PORT map(
-- Reset
......@@ -225,7 +261,7 @@ begin
txprgdivresetdone_out => open
);
inst_ethernet:ccn_eth_core
inst_ethernet:ccn_eth_core_0
PORT map(
s_axi_aresetn_0 => rst_n,
......@@ -378,31 +414,682 @@ begin
stat_tx_frame_error_0 => open
);
inst_reset_helper: entity ccn_eth_lib.ccn_ethernet_reset_wrapper
port map(
sys_reset => rst,
dclk => free_100_clk,
s_axi_aclk => axi_clk,
ctl_gt_reset_all => gt_rst_all,
ctl_gt_tx_reset => gt_rst_tx,
ctl_gt_rx_reset => gt_rst_rx,
gtwiz_reset_tx_datapath => tx_data_rst,
gtwiz_reset_rx_datapath => rx_data_rst,
gt_txusrclk2 => main_clk,
gt_rxusrclk2 => rxusrclk2,
rx_core_clk => main_clk,
gt_tx_reset_in => gtwiz_tx_rst_done,
gt_rx_reset_in => gtwiz_rx_rst_done,
tx_core_reset_in => tx_rst,
rx_core_reset_in => rx_rst,
tx_core_reset_out => tx_rst_core,
rx_core_reset_out => rx_rst_core,
rx_serdes_reset_out => rx_serdes_rst,
usr_tx_reset => open,
usr_rx_reset => open,
gtwiz_reset_all => gtwiz_reset_all,
gtwiz_reset_tx_datapath_out => gtwiz_rst_tx_datapath,
gtwiz_reset_rx_datapath_out => gtwiz_rst_rx_datapath
end generate G0;
G1:if G_IPNUM=1 generate
inst_gtwizard:ccn_gtwizard_1
PORT map(
-- Reset
gtwiz_reset_all_in(0) => gtwiz_reset_all,
gtwiz_userclk_rx_reset_in(0) => rx_clk_rst,
gtwiz_userclk_tx_reset_in(0) => tx_clk_rst,
gtwiz_reset_tx_done_out(0) => gtwiz_tx_rst_done,
gtwiz_reset_rx_done_out(0) => gtwiz_rx_rst_done,
gtwiz_reset_tx_datapath_in(0) => gtwiz_rst_tx_datapath,
gtwiz_reset_rx_datapath_in(0) => gtwiz_rst_rx_datapath,
-- Clocks
gtwiz_userclk_rx_usrclk2_out(0) => rxusrclk2,
gtwiz_userclk_tx_usrclk2_out(0) => main_clk,
-- Free run clock
gtwiz_reset_clk_freerun_in(0) => free_100_clk,
-- SFP
gthrxn_in(0) => sfp_rxn,
gthrxp_in(0) => sfp_rxp,
gthtxn_out(0) => sfp_txn,
gthtxp_out(0) => sfp_txp,
-- QPLL Common
qpll0clk_in(0) => qpll0clk_in,
qpll0refclk_in(0) => qpll0refclk_in,
gtwiz_reset_qpll0lock_in(0) => qpll0lock_in,
gtwiz_reset_qpll0reset_out(0) => qpll0reset_out,
-- SERDES
txdata_in => txdata,
rxdata_out => rxdata,
rxgearboxslip_in(0) => rxgearboxslip,
rxdatavalid_out => rxdatavalid,
rxheader_out => rxheader,
rxheadervalid_out => rxheadervalid,
txheader_in => txheader,
-- GT
loopback_in => gt_loopback,
--loopback_in(0) => '0',
--loopback_in(1) => gtloopback,
--loopback_in(2) => '0',
-- Status
gtwiz_userclk_tx_active_out(0) => tx_clk_active,
gtwiz_userclk_rx_active_out(0) => rx_clk_active,
gtpowergood_out(0) => gt_powergood,
gtwiz_reset_rx_cdr_stable_out(0) => cdr_stable,
-- Not used
txsequence_in => (others => '0'),
gtwiz_reset_tx_pll_and_datapath_in => "0",
gtwiz_reset_rx_pll_and_datapath_in => "0",
qpll1clk_in => "0",
qpll1refclk_in => "0",
gtwiz_userclk_tx_srcclk_out => open,
gtwiz_userclk_tx_usrclk_out => open,
gtwiz_userclk_rx_srcclk_out => open,
gtwiz_userclk_rx_usrclk_out => open,
rxpmaresetdone_out => open,
rxprgdivresetdone_out => open,
rxstartofseq_out => open,
txpmaresetdone_out => open,
txprgdivresetdone_out => open
);
inst_ethernet:ccn_eth_core_1
PORT map(
s_axi_aresetn_0 => rst_n,
-- GT reset
rx_reset_0 => rx_rst_core,
tx_reset_0 => tx_rst_core,
gtwiz_reset_tx_done_0 => gtwiz_tx_rst_done,
gtwiz_reset_rx_done_0 => gtwiz_rx_rst_done,
ctl_gt_reset_all_0 => gt_rst_all,
ctl_gt_tx_reset_0 => gt_rst_tx,
ctl_gt_rx_reset_0 => gt_rst_rx,
rx_serdes_reset_0 => rx_serdes_rst,
-- Clocks
rx_serdes_clk_0 => rxusrclk2,
rx_core_clk_0 => main_clk,
tx_core_clk_0 => main_clk,
-- SERDES
rx_serdes_data_out_0 => rxdata,
tx_serdes_data_in_0 => txdata,
rxgearboxslip_in_0 => rxgearboxslip,
rxdatavalid_out_0 => rxdatavalid,
rxheader_out_0 => rxheader,
rxheadervalid_out_0 => rxheadervalid,
txheader_in_0 => txheader,
-- GT
gt_loopback_out_0 => gtloopback,
-- AXI MM
s_axi_aclk_0 => axi_clk,
s_axi_awaddr_0(11 downto 0) => s_axi_awaddr,
s_axi_awaddr_0(31 downto 12) => (others => '0'),
s_axi_awvalid_0 => s_axi_awvalid,
s_axi_awready_0 => s_axi_awready,
s_axi_wdata_0 => s_axi_wdata,
s_axi_wstrb_0 => s_axi_wstrb,
s_axi_wvalid_0 => s_axi_wvalid,
s_axi_wready_0 => s_axi_wready,
s_axi_bresp_0 => s_axi_bresp,
s_axi_bvalid_0 => s_axi_bvalid,
s_axi_bready_0 => s_axi_bready,
s_axi_araddr_0(11 downto 0) => s_axi_araddr,
s_axi_araddr_0(31 downto 12) => (others => '0'),
s_axi_arvalid_0 => s_axi_arvalid,
s_axi_arready_0 => s_axi_arready,
s_axi_rdata_0 => s_axi_rdata,
s_axi_rresp_0 => s_axi_rresp,
s_axi_rvalid_0 => s_axi_rvalid,
s_axi_rready_0 => s_axi_rready,
-- AXI STREAM
rx_axis_tvalid_0 => rx_axis_tvalid,
rx_axis_tdata_0 => rx_axis_tdata,
rx_axis_tlast_0 => rx_axis_tlast,
rx_axis_tkeep_0 => rx_axis_tkeep,
rx_axis_tuser_0 => rx_axis_tuser,
tx_axis_tready_0 => tx_axis_tready,
tx_axis_tvalid_0 => tx_axis_tvalid,
tx_axis_tdata_0 => tx_axis_tdata,
tx_axis_tlast_0 => tx_axis_tlast,
tx_axis_tkeep_0 => tx_axis_tkeep,
tx_axis_tuser_0 => tx_axis_tuser,
-- Status
tx_unfout_0 => txunderflow,
user_reg0_0 => userreg,
-- Unused
tx_preamblein_0 => (others => '0'),
rx_preambleout_0 => open,
ctl_tx_send_rfi_0 => '0',
ctl_tx_send_lfi_0 => '0',
ctl_tx_send_idle_0 => '0',
-- Unused (stat)
pm_tick_0 => '0',
stat_rx_framing_err_0 => open,
stat_rx_framing_err_valid_0 => open,
stat_rx_local_fault_0 => open,
stat_rx_block_lock_0 => open,
stat_rx_valid_ctrl_code_0 => open,
stat_rx_status_0 => open,
stat_rx_remote_fault_0 => open,
stat_rx_bad_fcs_0 => open,
stat_rx_stomped_fcs_0 => open,
stat_rx_truncated_0 => open,
stat_rx_internal_local_fault_0 => open,
stat_rx_received_local_fault_0 => open,
stat_rx_hi_ber_0 => open,
stat_rx_got_signal_os_0 => open,
stat_rx_test_pattern_mismatch_0 => open,
stat_rx_total_bytes_0 => open,
stat_rx_total_packets_0 => open,
stat_rx_total_good_bytes_0 => open,
stat_rx_total_good_packets_0 => open,
stat_rx_packet_bad_fcs_0 => open,
stat_rx_packet_64_bytes_0 => open,
stat_rx_packet_65_127_bytes_0 => open,
stat_rx_packet_128_255_bytes_0 => open,
stat_rx_packet_256_511_bytes_0 => open,
stat_rx_packet_512_1023_bytes_0 => open,
stat_rx_packet_1024_1518_bytes_0 => open,
stat_rx_packet_1519_1522_bytes_0 => open,
stat_rx_packet_1523_1548_bytes_0 => open,
stat_rx_packet_1549_2047_bytes_0 => open,
stat_rx_packet_2048_4095_bytes_0 => open,
stat_rx_packet_4096_8191_bytes_0 => open,
stat_rx_packet_8192_9215_bytes_0 => open,
stat_rx_packet_small_0 => open,
stat_rx_packet_large_0 => open,
stat_rx_unicast_0 => open,
stat_rx_multicast_0 => open,
stat_rx_broadcast_0 => open,
stat_rx_oversize_0 => open,
stat_rx_toolong_0 => open,
stat_rx_undersize_0 => open,
stat_rx_fragment_0 => open,
stat_rx_vlan_0 => open,
stat_rx_inrangeerr_0 => open,
stat_rx_jabber_0 => open,
stat_rx_bad_code_0 => open,
stat_rx_bad_sfd_0 => open,
stat_rx_bad_preamble_0 => open,
stat_tx_local_fault_0 => open,
stat_tx_total_bytes_0 => open,
stat_tx_total_packets_0 => open,
stat_tx_total_good_bytes_0 => open,
stat_tx_total_good_packets_0 => open,
stat_tx_bad_fcs_0 => open,
stat_tx_packet_64_bytes_0 => open,
stat_tx_packet_65_127_bytes_0 => open,
stat_tx_packet_128_255_bytes_0 => open,
stat_tx_packet_256_511_bytes_0 => open,
stat_tx_packet_512_1023_bytes_0 => open,
stat_tx_packet_1024_1518_bytes_0 => open,
stat_tx_packet_1519_1522_bytes_0 => open,
stat_tx_packet_1523_1548_bytes_0 => open,
stat_tx_packet_1549_2047_bytes_0 => open,
stat_tx_packet_2048_4095_bytes_0 => open,
stat_tx_packet_4096_8191_bytes_0 => open,
stat_tx_packet_8192_9215_bytes_0 => open,
stat_tx_packet_small_0 => open,
stat_tx_packet_large_0 => open,
stat_tx_unicast_0 => open,
stat_tx_multicast_0 => open,
stat_tx_broadcast_0 => open,
stat_tx_vlan_0 => open,
stat_tx_frame_error_0 => open
);
end generate G1;
G2:if G_IPNUM=2 generate
inst_gtwizard:ccn_gtwizard_2
PORT map(
-- Reset
gtwiz_reset_all_in(0) => gtwiz_reset_all,
gtwiz_userclk_rx_reset_in(0) => rx_clk_rst,
gtwiz_userclk_tx_reset_in(0) => tx_clk_rst,
gtwiz_reset_tx_done_out(0) => gtwiz_tx_rst_done,
gtwiz_reset_rx_done_out(0) => gtwiz_rx_rst_done,
gtwiz_reset_tx_datapath_in(0) => gtwiz_rst_tx_datapath,
gtwiz_reset_rx_datapath_in(0) => gtwiz_rst_rx_datapath,
-- Clocks
gtwiz_userclk_rx_usrclk2_out(0) => rxusrclk2,
gtwiz_userclk_tx_usrclk2_out(0) => main_clk,
-- Free run clock
gtwiz_reset_clk_freerun_in(0) => free_100_clk,
-- SFP
gthrxn_in(0) => sfp_rxn,
gthrxp_in(0) => sfp_rxp,
gthtxn_out(0) => sfp_txn,
gthtxp_out(0) => sfp_txp,
-- QPLL Common
qpll0clk_in(0) => qpll0clk_in,
qpll0refclk_in(0) => qpll0refclk_in,
gtwiz_reset_qpll0lock_in(0) => qpll0lock_in,
gtwiz_reset_qpll0reset_out(0) => qpll0reset_out,
-- SERDES
txdata_in => txdata,
rxdata_out => rxdata,
rxgearboxslip_in(0) => rxgearboxslip,
rxdatavalid_out => rxdatavalid,
rxheader_out => rxheader,
rxheadervalid_out => rxheadervalid,
txheader_in => txheader,
-- GT
loopback_in => gt_loopback,
--loopback_in(0) => '0',
--loopback_in(1) => gtloopback,
--loopback_in(2) => '0',
-- Status
gtwiz_userclk_tx_active_out(0) => tx_clk_active,
gtwiz_userclk_rx_active_out(0) => rx_clk_active,
gtpowergood_out(0) => gt_powergood,
gtwiz_reset_rx_cdr_stable_out(0) => cdr_stable,
-- Not used
txsequence_in => (others => '0'),
gtwiz_reset_tx_pll_and_datapath_in => "0",
gtwiz_reset_rx_pll_and_datapath_in => "0",
qpll1clk_in => "0",
qpll1refclk_in => "0",
gtwiz_userclk_tx_srcclk_out => open,
gtwiz_userclk_tx_usrclk_out => open,
gtwiz_userclk_rx_srcclk_out => open,
gtwiz_userclk_rx_usrclk_out => open,
rxpmaresetdone_out => open,
rxprgdivresetdone_out => open,
rxstartofseq_out => open,
txpmaresetdone_out => open,
txprgdivresetdone_out => open
);
inst_ethernet:ccn_eth_core_2
PORT map(
s_axi_aresetn_0 => rst_n,
-- GT reset
rx_reset_0 => rx_rst_core,
tx_reset_0 => tx_rst_core,
gtwiz_reset_tx_done_0 => gtwiz_tx_rst_done,
gtwiz_reset_rx_done_0 => gtwiz_rx_rst_done,
ctl_gt_reset_all_0 => gt_rst_all,
ctl_gt_tx_reset_0 => gt_rst_tx,
ctl_gt_rx_reset_0 => gt_rst_rx,
rx_serdes_reset_0 => rx_serdes_rst,
-- Clocks
rx_serdes_clk_0 => rxusrclk2,
rx_core_clk_0 => main_clk,
tx_core_clk_0 => main_clk,
-- SERDES
rx_serdes_data_out_0 => rxdata,
tx_serdes_data_in_0 => txdata,
rxgearboxslip_in_0 => rxgearboxslip,
rxdatavalid_out_0 => rxdatavalid,
rxheader_out_0 => rxheader,
rxheadervalid_out_0 => rxheadervalid,
txheader_in_0 => txheader,
-- GT
gt_loopback_out_0 => gtloopback,
-- AXI MM
s_axi_aclk_0 => axi_clk,
s_axi_awaddr_0(11 downto 0) => s_axi_awaddr,
s_axi_awaddr_0(31 downto 12) => (others => '0'),
s_axi_awvalid_0 => s_axi_awvalid,
s_axi_awready_0 => s_axi_awready,
s_axi_wdata_0 => s_axi_wdata,
s_axi_wstrb_0 => s_axi_wstrb,
s_axi_wvalid_0 => s_axi_wvalid,
s_axi_wready_0 => s_axi_wready,
s_axi_bresp_0 => s_axi_bresp,
s_axi_bvalid_0 => s_axi_bvalid,
s_axi_bready_0 => s_axi_bready,
s_axi_araddr_0(11 downto 0) => s_axi_araddr,
s_axi_araddr_0(31 downto 12) => (others => '0'),
s_axi_arvalid_0 => s_axi_arvalid,
s_axi_arready_0 => s_axi_arready,
s_axi_rdata_0 => s_axi_rdata,
s_axi_rresp_0 => s_axi_rresp,
s_axi_rvalid_0 => s_axi_rvalid,
s_axi_rready_0 => s_axi_rready,
-- AXI STREAM
rx_axis_tvalid_0 => rx_axis_tvalid,
rx_axis_tdata_0 => rx_axis_tdata,
rx_axis_tlast_0 => rx_axis_tlast,
rx_axis_tkeep_0 => rx_axis_tkeep,
rx_axis_tuser_0 => rx_axis_tuser,
tx_axis_tready_0 => tx_axis_tready,
tx_axis_tvalid_0 => tx_axis_tvalid,
tx_axis_tdata_0 => tx_axis_tdata,
tx_axis_tlast_0 => tx_axis_tlast,
tx_axis_tkeep_0 => tx_axis_tkeep,
tx_axis_tuser_0 => tx_axis_tuser,
-- Status
tx_unfout_0 => txunderflow,
user_reg0_0 => userreg,
-- Unused
tx_preamblein_0 => (others => '0'),
rx_preambleout_0 => open,
ctl_tx_send_rfi_0 => '0',
ctl_tx_send_lfi_0 => '0',
ctl_tx_send_idle_0 => '0',
-- Unused (stat)
pm_tick_0 => '0',
stat_rx_framing_err_0 => open,
stat_rx_framing_err_valid_0 => open,
stat_rx_local_fault_0 => open,
stat_rx_block_lock_0 => open,
stat_rx_valid_ctrl_code_0 => open,
stat_rx_status_0 => open,
stat_rx_remote_fault_0 => open,
stat_rx_bad_fcs_0 => open,
stat_rx_stomped_fcs_0 => open,
stat_rx_truncated_0 => open,
stat_rx_internal_local_fault_0 => open,
stat_rx_received_local_fault_0 => open,
stat_rx_hi_ber_0 => open,
stat_rx_got_signal_os_0 => open,
stat_rx_test_pattern_mismatch_0 => open,
stat_rx_total_bytes_0 => open,
stat_rx_total_packets_0 => open,
stat_rx_total_good_bytes_0 => open,
stat_rx_total_good_packets_0 => open,
stat_rx_packet_bad_fcs_0 => open,
stat_rx_packet_64_bytes_0 => open,
stat_rx_packet_65_127_bytes_0 => open,
stat_rx_packet_128_255_bytes_0 => open,
stat_rx_packet_256_511_bytes_0 => open,
stat_rx_packet_512_1023_bytes_0 => open,
stat_rx_packet_1024_1518_bytes_0 => open,
stat_rx_packet_1519_1522_bytes_0 => open,
stat_rx_packet_1523_1548_bytes_0 => open,
stat_rx_packet_1549_2047_bytes_0 => open,
stat_rx_packet_2048_4095_bytes_0 => open,
stat_rx_packet_4096_8191_bytes_0 => open,
stat_rx_packet_8192_9215_bytes_0 => open,
stat_rx_packet_small_0 => open,
stat_rx_packet_large_0 => open,
stat_rx_unicast_0 => open,
stat_rx_multicast_0 => open,
stat_rx_broadcast_0 => open,
stat_rx_oversize_0 => open,
stat_rx_toolong_0 => open,
stat_rx_undersize_0 => open,
stat_rx_fragment_0 => open,
stat_rx_vlan_0 => open,
stat_rx_inrangeerr_0 => open,
stat_rx_jabber_0 => open,
stat_rx_bad_code_0 => open,
stat_rx_bad_sfd_0 => open,
stat_rx_bad_preamble_0 => open,
stat_tx_local_fault_0 => open,
stat_tx_total_bytes_0 => open,
stat_tx_total_packets_0 => open,
stat_tx_total_good_bytes_0 => open,
stat_tx_total_good_packets_0 => open,
stat_tx_bad_fcs_0 => open,
stat_tx_packet_64_bytes_0 => open,
stat_tx_packet_65_127_bytes_0 => open,
stat_tx_packet_128_255_bytes_0 => open,
stat_tx_packet_256_511_bytes_0 => open,
stat_tx_packet_512_1023_bytes_0 => open,
stat_tx_packet_1024_1518_bytes_0 => open,
stat_tx_packet_1519_1522_bytes_0 => open,
stat_tx_packet_1523_1548_bytes_0 => open,
stat_tx_packet_1549_2047_bytes_0 => open,
stat_tx_packet_2048_4095_bytes_0 => open,
stat_tx_packet_4096_8191_bytes_0 => open,
stat_tx_packet_8192_9215_bytes_0 => open,
stat_tx_packet_small_0 => open,
stat_tx_packet_large_0 => open,
stat_tx_unicast_0 => open,
stat_tx_multicast_0 => open,
stat_tx_broadcast_0 => open,
stat_tx_vlan_0 => open,
stat_tx_frame_error_0 => open
);
end generate G2;
G3:if G_IPNUM=3 generate
inst_gtwizard:ccn_gtwizard_3
PORT map(
-- Reset
gtwiz_reset_all_in(0) => gtwiz_reset_all,
gtwiz_userclk_rx_reset_in(0) => rx_clk_rst,
gtwiz_userclk_tx_reset_in(0) => tx_clk_rst,
gtwiz_reset_tx_done_out(0) => gtwiz_tx_rst_done,
gtwiz_reset_rx_done_out(0) => gtwiz_rx_rst_done,
gtwiz_reset_tx_datapath_in(0) => gtwiz_rst_tx_datapath,
gtwiz_reset_rx_datapath_in(0) => gtwiz_rst_rx_datapath,
-- Clocks
gtwiz_userclk_rx_usrclk2_out(0) => rxusrclk2,
gtwiz_userclk_tx_usrclk2_out(0) => main_clk,
-- Free run clock
gtwiz_reset_clk_freerun_in(0) => free_100_clk,
-- SFP
gthrxn_in(0) => sfp_rxn,
gthrxp_in(0) => sfp_rxp,
gthtxn_out(0) => sfp_txn,
gthtxp_out(0) => sfp_txp,
-- QPLL Common
qpll0clk_in(0) => qpll0clk_in,
qpll0refclk_in(0) => qpll0refclk_in,
gtwiz_reset_qpll0lock_in(0) => qpll0lock_in,
gtwiz_reset_qpll0reset_out(0) => qpll0reset_out,
-- SERDES
txdata_in => txdata,
rxdata_out => rxdata,
rxgearboxslip_in(0) => rxgearboxslip,
rxdatavalid_out => rxdatavalid,
rxheader_out => rxheader,
rxheadervalid_out => rxheadervalid,
txheader_in => txheader,
-- GT
loopback_in => gt_loopback,
--loopback_in(0) => '0',
--loopback_in(1) => gtloopback,
--loopback_in(2) => '0',
-- Status
gtwiz_userclk_tx_active_out(0) => tx_clk_active,
gtwiz_userclk_rx_active_out(0) => rx_clk_active,
gtpowergood_out(0) => gt_powergood,
gtwiz_reset_rx_cdr_stable_out(0) => cdr_stable,
-- Not used
txsequence_in => (others => '0'),
gtwiz_reset_tx_pll_and_datapath_in => "0",
gtwiz_reset_rx_pll_and_datapath_in => "0",
qpll1clk_in => "0",
qpll1refclk_in => "0",
gtwiz_userclk_tx_srcclk_out => open,
gtwiz_userclk_tx_usrclk_out => open,
gtwiz_userclk_rx_srcclk_out => open,
gtwiz_userclk_rx_usrclk_out => open,
rxpmaresetdone_out => open,
rxprgdivresetdone_out => open,
rxstartofseq_out => open,
txpmaresetdone_out => open,
txprgdivresetdone_out => open
);
inst_ethernet:ccn_eth_core_3
PORT map(
s_axi_aresetn_0 => rst_n,
-- GT reset
rx_reset_0 => rx_rst_core,
tx_reset_0 => tx_rst_core,
gtwiz_reset_tx_done_0 => gtwiz_tx_rst_done,
gtwiz_reset_rx_done_0 => gtwiz_rx_rst_done,
ctl_gt_reset_all_0 => gt_rst_all,
ctl_gt_tx_reset_0 => gt_rst_tx,
ctl_gt_rx_reset_0 => gt_rst_rx,
rx_serdes_reset_0 => rx_serdes_rst,
-- Clocks
rx_serdes_clk_0 => rxusrclk2,
rx_core_clk_0 => main_clk,
tx_core_clk_0 => main_clk,
-- SERDES
rx_serdes_data_out_0 => rxdata,
tx_serdes_data_in_0 => txdata,
rxgearboxslip_in_0 => rxgearboxslip,
rxdatavalid_out_0 => rxdatavalid,
rxheader_out_0 => rxheader,
rxheadervalid_out_0 => rxheadervalid,
txheader_in_0 => txheader,
-- GT
gt_loopback_out_0 => gtloopback,
-- AXI MM
s_axi_aclk_0 => axi_clk,
s_axi_awaddr_0(11 downto 0) => s_axi_awaddr,
s_axi_awaddr_0(31 downto 12) => (others => '0'),
s_axi_awvalid_0 => s_axi_awvalid,
s_axi_awready_0 => s_axi_awready,
s_axi_wdata_0 => s_axi_wdata,
s_axi_wstrb_0 => s_axi_wstrb,
s_axi_wvalid_0 => s_axi_wvalid,
s_axi_wready_0 => s_axi_wready,
s_axi_bresp_0 => s_axi_bresp,
s_axi_bvalid_0 => s_axi_bvalid,
s_axi_bready_0 => s_axi_bready,
s_axi_araddr_0(11 downto 0) => s_axi_araddr,
s_axi_araddr_0(31 downto 12) => (others => '0'),
s_axi_arvalid_0 => s_axi_arvalid,
s_axi_arready_0 => s_axi_arready,
s_axi_rdata_0 => s_axi_rdata,
s_axi_rresp_0 => s_axi_rresp,
s_axi_rvalid_0 => s_axi_rvalid,
s_axi_rready_0 => s_axi_rready,
-- AXI STREAM
rx_axis_tvalid_0 => rx_axis_tvalid,
rx_axis_tdata_0 => rx_axis_tdata,
rx_axis_tlast_0 => rx_axis_tlast,
rx_axis_tkeep_0 => rx_axis_tkeep,
rx_axis_tuser_0 => rx_axis_tuser,
tx_axis_tready_0 => tx_axis_tready,
tx_axis_tvalid_0 => tx_axis_tvalid,
tx_axis_tdata_0 => tx_axis_tdata,
tx_axis_tlast_0 => tx_axis_tlast,
tx_axis_tkeep_0 => tx_axis_tkeep,
tx_axis_tuser_0 => tx_axis_tuser,
-- Status
tx_unfout_0 => txunderflow,
user_reg0_0 => userreg,
-- Unused
tx_preamblein_0 => (others => '0'),
rx_preambleout_0 => open,
ctl_tx_send_rfi_0 => '0',
ctl_tx_send_lfi_0 => '0',
ctl_tx_send_idle_0 => '0',
-- Unused (stat)
pm_tick_0 => '0',
stat_rx_framing_err_0 => open,
stat_rx_framing_err_valid_0 => open,
stat_rx_local_fault_0 => open,
stat_rx_block_lock_0 => open,
stat_rx_valid_ctrl_code_0 => open,
stat_rx_status_0 => open,
stat_rx_remote_fault_0 => open,
stat_rx_bad_fcs_0 => open,
stat_rx_stomped_fcs_0 => open,
stat_rx_truncated_0 => open,
stat_rx_internal_local_fault_0 => open,
stat_rx_received_local_fault_0 => open,
stat_rx_hi_ber_0 => open,
stat_rx_got_signal_os_0 => open,
stat_rx_test_pattern_mismatch_0 => open,
stat_rx_total_bytes_0 => open,
stat_rx_total_packets_0 => open,
stat_rx_total_good_bytes_0 => open,
stat_rx_total_good_packets_0 => open,
stat_rx_packet_bad_fcs_0 => open,
stat_rx_packet_64_bytes_0 => open,
stat_rx_packet_65_127_bytes_0 => open,
stat_rx_packet_128_255_bytes_0 => open,
stat_rx_packet_256_511_bytes_0 => open,
stat_rx_packet_512_1023_bytes_0 => open,
stat_rx_packet_1024_1518_bytes_0 => open,
stat_rx_packet_1519_1522_bytes_0 => open,
stat_rx_packet_1523_1548_bytes_0 => open,
stat_rx_packet_1549_2047_bytes_0 => open,
stat_rx_packet_2048_4095_bytes_0 => open,
stat_rx_packet_4096_8191_bytes_0 => open,
stat_rx_packet_8192_9215_bytes_0 => open,
stat_rx_packet_small_0 => open,
stat_rx_packet_large_0 => open,
stat_rx_unicast_0 => open,
stat_rx_multicast_0 => open,
stat_rx_broadcast_0 => open,
stat_rx_oversize_0 => open,
stat_rx_toolong_0 => open,
stat_rx_undersize_0 => open,
stat_rx_fragment_0 => open,
stat_rx_vlan_0 => open,
stat_rx_inrangeerr_0 => open,
stat_rx_jabber_0 => open,
stat_rx_bad_code_0 => open,
stat_rx_bad_sfd_0 => open,
stat_rx_bad_preamble_0 => open,
stat_tx_local_fault_0 => open,
stat_tx_total_bytes_0 => open,
stat_tx_total_packets_0 => open,
stat_tx_total_good_bytes_0 => open,
stat_tx_total_good_packets_0 => open,
stat_tx_bad_fcs_0 => open,
stat_tx_packet_64_bytes_0 => open,
stat_tx_packet_65_127_bytes_0 => open,
stat_tx_packet_128_255_bytes_0 => open,
stat_tx_packet_256_511_bytes_0 => open,
stat_tx_packet_512_1023_bytes_0 => open,
stat_tx_packet_1024_1518_bytes_0 => open,
stat_tx_packet_1519_1522_bytes_0 => open,
stat_tx_packet_1523_1548_bytes_0 => open,
stat_tx_packet_1549_2047_bytes_0 => open,
stat_tx_packet_2048_4095_bytes_0 => open,
stat_tx_packet_4096_8191_bytes_0 => open,
stat_tx_packet_8192_9215_bytes_0 => open,
stat_tx_packet_small_0 => open,
stat_tx_packet_large_0 => open,
stat_tx_unicast_0 => open,
stat_tx_multicast_0 => open,
stat_tx_broadcast_0 => open,
stat_tx_vlan_0 => open,
stat_tx_frame_error_0 => open
);
end generate G3;
end architecture struct;
......@@ -11,6 +11,9 @@ use ccn_eth_lib.pkg_ccn_ethernet.all;
use ccn_eth_lib.pkg_ccn_ethernet_version.all;
entity top_ccn_ethernet is
generic(
G_IPNUM : natural := 0
);
port(
aresetn : in std_logic;
axis_clk : out std_logic;
......@@ -85,6 +88,7 @@ begin
-- ETHERNET --
--------------
inst_ethernet:entity ccn_eth_lib.ccn_ethernet
generic map(G_IPNUM => G_IPNUM)
port map(
free_100_clk => free_100_clk,
axi_clk => aclk,
......
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