Wip:Rename to CCN, add 4 component declaration

hdl/comcellnode_ethernet.vhd → hdl/ccn_ethernet.vhd

 library ieee;
 use ieee.std_logic_1164.all;
 
-use work.pkg_cc_ethernet.all;
+library ccn_eth_lib;
+use ccn_eth_lib.pkg_ccn_ethernet.all;
 
-entity comcellnode_ethernet is
+entity ccn_ethernet is
     port(
         free_100_clk                       : in std_logic;
         axi_clk                            : in std_logic;
@@ -77,9 +78,9 @@ entity comcellnode_ethernet is
         s_axi_rready                       : IN STD_LOGIC
 
         );
-end entity comcellnode_ethernet;
+end entity ccn_ethernet;
 
-architecture struct of comcellnode_ethernet is
+architecture struct of ccn_ethernet is
 
     --------------------------
     -- INTERFACE ATTRIBUTES --
@@ -377,7 +378,7 @@ begin
         stat_tx_frame_error_0            => open
     );
 
-    inst_reset_helper: entity work.comcellnode_ethernet_reset_wrapper
+    inst_reset_helper: entity ccn_eth_lib.ccn_ethernet_reset_wrapper
     port map(
         sys_reset                   => rst,
         dclk                        => free_100_clk,

hdl/comcellnode_ethernet_reset_wrapper.v → hdl/ccn_ethernet_reset_wrapper.v

@@ -59,7 +59,7 @@
 
 `timescale 1ps / 1ps
 (* DowngradeIPIdentifiedWarnings="yes" *)
-module comcellnode_ethernet_reset_wrapper
+module ccn_ethernet_reset_wrapper
 (
     input  wire sys_reset,
     input  wire dclk,

hdl/top_comcellnode_ethernet.vhd → hdl/top_ccn_ethernet.vhd

@@ -4,11 +4,13 @@ use ieee.numeric_std.all;
 
 library desyrdl;
 use desyrdl.common.all;
-use desyrdl.pkg_comcellnode_ethernet.all;
+use desyrdl.pkg_ccn_ethernet.all;
 
-use work.pkg_comcellnode_ethernet_version.all;
+library ccn_eth_lib;
+use ccn_eth_lib.pkg_ccn_ethernet.all;
+use ccn_eth_lib.pkg_ccn_ethernet_version.all;
 
-entity top_comcellnode_ethernet is
+entity top_ccn_ethernet is
     port(
         aresetn                     : in std_logic;
         axis_clk                    : out std_logic;
@@ -22,8 +24,8 @@ entity top_comcellnode_ethernet is
         qpll0reset_out              : out std_logic;
 
         -- AXI-MM Status and Config
-        s_axi_m2s                   : in  t_comcellnode_ethernet_m2s;
-        s_axi_s2m                   : out t_comcellnode_ethernet_s2m;
+        s_axi_m2s                   : in  t_ccn_ethernet_m2s;
+        s_axi_s2m                   : out t_ccn_ethernet_s2m;
 
         -- AXIS TX RX
         s_axis_tx_tvalid            : in std_logic;
@@ -49,15 +51,15 @@ entity top_comcellnode_ethernet is
         sfp_tx_fault                : in std_logic
 
     );
-end entity top_comcellnode_ethernet;
+end entity top_ccn_ethernet;
 
-architecture rtl of top_comcellnode_ethernet is
+architecture rtl of top_ccn_ethernet is
 
     ------------------------
     -- SIGNAL DECLARATION --
     ------------------------
-    signal addrmap_i           : t_addrmap_comcellnode_ethernet_in;
-    signal addrmap_o           : t_addrmap_comcellnode_ethernet_out;
+    signal addrmap_i           : t_addrmap_ccn_ethernet_in;
+    signal addrmap_o           : t_addrmap_ccn_ethernet_out;
     signal areset              : std_logic;
 
 begin
@@ -67,7 +69,7 @@ begin
     ----------------------
     -- AXI-MM INTERFACE --
     ----------------------
-    inst_aximm: entity desyrdl.comcellnode_ethernet
+    inst_aximm: entity desyrdl.ccn_ethernet
     port map(
         pi_clock    => aclk,
         pi_reset    => areset,
@@ -82,7 +84,7 @@ begin
     --------------
     -- ETHERNET --
     --------------
-    inst_ethernet:entity work.comcellnode_ethernet
+    inst_ethernet:entity ccn_eth_lib.ccn_ethernet
     port map(
         free_100_clk                       => free_100_clk,
         axi_clk                            => aclk,

rdl/comcellnode_ethernet.rdl → rdl/ccn_ethernet.rdl

-`include "comcellnode_ethernet.vh"
+`include "ccn_ethernet.vh"
 
-addrmap comcellnode_ethernet {
+addrmap ccn_ethernet {
 
     desyrdl_generate_hdl = true;
     desyrdl_interface = "AXI4L";

tcl/main.tcl

@@ -12,36 +12,33 @@ proc init {} {
 
 # ==============================================================================
 proc setSources {} {
-  variable Vhdl
-  variable Verilog
+    variable Sources
 
     # Generate VHDL package with modle version
-  genModVerFile VHDL ../hdl/pkg_comcellnode_ethernet_version.vhd
+    genModVerFile VHDL ../hdl/pkg_ccn_ethernet_version.vhd
 
-  lappend Vhdl ../hdl/comcellnode_ethernet.vhd
-  lappend Vhdl ../hdl/top_comcellnode_ethernet.vhd
-  lappend Vhdl ../hdl/pkg_comcellnode_ethernet_version.vhd
-  lappend Vhdl ../hdl/pkg_ccn_ethernet.vhd
-
-  lappend Verilog ../hdl/comcellnode_ethernet_reset_wrapper.v
+    # {SrcFile SrcType srcLib usedIn procOrder}
+    lappend Sources {"../hdl/top_ccn_ethernet.vhd"          "VHDL"      "ccn_eth_lib"}
+    lappend Sources {"../hdl/ccn_ethernet.vhd"              "VHDL"      "ccn_eth_lib"}
+    lappend Sources {"../hdl/pkg_ccn_ethernet.vhd"          "VHDL"      "ccn_eth_lib"}
+    lappend Sources {"../hdl/pkg_ccn_ethernet_version.vhd"  "VHDL"      "ccn_eth_lib"}
+    lappend Sources {"../hdl/ccn_ethernet_reset_wrapper.v"  "verilog"   "ccn_eth_lib"}
 
 }
 
 # ==============================================================================
 proc setAddressSpace {} {
     variable AddressSpace
-    addAddressSpace AddressSpace "comcellnode_ethernet" RDL {} ../rdl/comcellnode_ethernet.rdl
+    addAddressSpace AddressSpace "ccn_ethernet" RDL {} ../rdl/ccn_ethernet.rdl
     addAddressSpace AddressSpace "xilinx_ethsubsyst" RDL {} ../rdl/xilinx_ethsubsyst.rdl
 }
 
 # ==============================================================================
 proc doOnCreate {} {
-  variable Vhdl
-  variable Verilog
+  variable Sources
   variable Config
 
-  addSources Vhdl
-  addSources Verilog
+  addSources Sources
 
   set idx 0
   foreach GTH_LOC $Config(GTH_LOC) {