* Also change the name of the table.
* DESYRDL right shift the address by 2 before passing it to the memory.
  This is equivalent of having element of 32bits.

* Update doc with recent changes (Clock, filter)
* Module ID is now hardcoded in RDL

* Or else DESYRDL gives only 9 bits to the decoder, which collides with
the 8 bits address of the table (counted from the 2nd lesser bit)

* Packet filter now uses DESYLIB true dual port RAM.
* Add a packet filter before the module output.
* Add packet filter as external memory in rdl.

* Add a README proxy to doc/main.adoc
* Include adoc generated by desyrdl for the register map.
* Frame counters and rates were not linked to the addrmap. Fix that.
* Add description for registers and fields in RDL

* Also remove the ID field

* Update documentation
* Top level uses bpmframe stream package
* Remove unused files (quad common will be moved in application)
* Capitalization killer for RDL file ;)
* Change package version name, decomment the C_ID and C_Version for the
  AXI-MM registers.

* Rename the RDL file, and the addrmap name to match the module name.
* Add addAddressSpace that gives the RDL file path.

* Reset the register properly
* Add register in memory map bank

Top level:
* Add MC time and PPS port
* GT Interface ready combinatorial inside top level

Protocol decoder
* New GT Interface ready input port
* New MC time and PPS input ports
* New output ports for new features
* Frame counters, frame rates
* Sequence checkers
* Change output AXIS packet : MC time, packet_time LSB only

AXI interface:
* Add registers for new features
* Fix Makefile rule for RDL->VHD

* Add debug ports of transceiver data and status before the protocole
  decoder.
* Add a reset bit for PLL and datapath in AXI-MM interface.

* Remove unused signals

* GTHE COMMON must be outside IP (QPLL needed for other interfaces)
* GTWizard created with TCL
* GTWizard instantiated directly in top level

* Import sources from Cell Node initial project