New AXIMM register layout, fix CDC for PPS

* A CDC is now used for PPS input. Fixes double PPS trig and hence rate seen as 0 !! This implies that the PPS signal is at least 2 inner clock cycle long * Break sw R/RW registers, for OPCUA/ChimeraTK compatibility

New AXIMM register layout, fix CDC for PPS
3b898d76 · BRONES Romain · 0aaa7af0 · 1c323922 · 3b898d76 · 3b898d76
Commit 3b898d76 authored 1 year ago by BRONES Romain
--- a/doc/regmap.adoc
+++ b/doc/regmap.adoc
@@ -3,34 +3,35 @@
 |===
 |Name | N | bits | type | RW | Description
-| ID                                       |    1 |   32 | uint |   RO | +++Module identifier.+++  
+| ID                                       |    1 |   32 |     uint | RO | +++Module Identification Number+++ +
-| VERSION                                  |    1 |   32 | uint |   RO | +++Module version.+++  
+| VERSION                                  |    1 |   32 |     uint | RO | +++Module version.+++ +
 | SFP                                      |    1 |    2 | bitfields |   RO | +++SFP module status+++   +
- RXLOS [0:0] sw:RO uint : +++RX lost signal+++  +
+    _RXLOS_ [0:0] sw:RO uint : +++RX lost signal+++ +
- MODABS [1:1] sw:RO uint : +++Module is absent+++   
+    _MODABS_ [1:1] sw:RO uint : +++Module is absent+++ +
-| GT                                       |    1 |   11 | bitfields |   RW | +++GT transceivers status and control+++   +
+| GT_STATUS                                |    1 |    8 | bitfields | RO | +++GT transceivers status+++ +
- POWERGOOD [0:0] sw:RO uint : +++Powergood signal+++  +
+    _POWERGOOD_ [0:0] sw:RO uint : +++Powergood signal+++ +
- QPLLLOCK [1:1] sw:RO uint : +++PLL lock signal+++  +
+    _QPLLLOCK_ [1:1] sw:RO uint : +++PLL lock signal+++ +
- RXCLKACTIVE [2:2] sw:RO uint : +++RX clk active signal+++  +
+    _RXCLKACTIVE_ [2:2] sw:RO uint : +++RX clk active signal+++ +
- RXCDRLOCK [3:3] sw:RO uint : +++RX CDR lock signal+++  +
+    _RXCDRLOCK_ [3:3] sw:RO uint : +++RX CDR lock signal+++ +
- RXRESETDONE [4:4] sw:RO uint : +++RX reset done signal+++  +
+    _RXRESETDONE_ [4:4] sw:RO uint : +++RX reset done signal+++ +
- RXBYTEISALIGNED [5:5] sw:RO uint : +++RX byte is aligned signal+++  +
+    _RXBYTEISALIGNED_ [5:5] sw:RO uint : +++RX byte is aligned signal+++ +
- RXBYTEREALIGN [6:6] sw:RO uint : +++RX byte realign signal+++  +
+    _RXBYTEREALIGN_ [6:6] sw:RO uint : +++RX byte realign signal+++ +
- RXCOMMADET [7:7] sw:RO uint : +++RX comma detected signal+++  +
+    _RXCOMMADET_ [7:7] sw:RO uint : +++RX comma detected signal+++ +
- RXCOMMADETEN [8:8] sw:RW uint : +++RX comma detection enable signal+++  +
+| GT_CONTROL                               |    1 |    3 | bitfields | RW | +++GT transceivers control+++ +
- RXRSTDATAPATH [9:9] sw:RW uint : +++Reset RX datapath+++  +
+    _RXCOMMADETEN_ [0:0] sw:RW uint : +++RX comma detection enable signal+++ +
- RXRSTPLLDATAPATH [10:10] sw:RW uint : +++Reset RX PLL and datapath+++   
+    _RXRSTDATAPATH_ [1:1] sw:RW uint : +++Reset RX datapath+++ +
-| PROTOCOL                                 |    1 |    4 | bitfields |   RW | +++BPM protocol status and control+++   +
+    _RXRSTPLLDATAPATH_ [2:2] sw:RW uint : +++Reset RX PLL and datapath+++ +
- FRAMEERROR [0:0] sw:RO uint : +++Frame error+++  +
+| PROTOCOL_ERROR                           |    1 |    3 | bitfields | RO | +++BPM protocol status and control+++ +
- SEQFRAMECNTERROR [1:1] sw:RO uint : +++Sequence frame count mismatch+++  +
+    _FRAMEERROR_ [0:0] sw:RO uint : +++Frame error+++ +
- SEQFRAMEDISCONT [2:2] sw:RO uint : +++Sequence frame discontinuity+++  +
+    _SEQFRAMECNTERROR_ [1:1] sw:RO uint : +++Sequence frame count mismatch+++ +
- SOFTRESET [3:3] sw:RW uint : +++Soft reset+++   
+    _SEQFRAMEDISCONT_ [2:2] sw:RO uint : +++Sequence frame discontinuity+++ +
-| VALIDFRAMECNT                            |    1 |   32 | uint |   RO | +++BPM protocol valid frame counters+++  
+| RESET                                    |    1 |    1 |     uint | RW | +++None+++ +
-| INVALIDFRAMECNT                          |    1 |   32 | uint |   RO | +++BPM protocol invalid frame counters+++  
+| VALIDFRAMECNT                            |    1 |   32 |     uint | RO | +++BPM protocol valid frame counters+++ +
-| VALIDFRAMERATE                           |    1 |   32 | uint |   RO | +++BPM protocol valid frame rate+++  
+| INVALIDFRAMECNT                          |    1 |   32 |     uint | RO | +++BPM protocol invalid frame counters+++ +
-| INVALIDFRAMERATE                         |    1 |   32 | uint |   RO | +++BPM protocol invalid frame rate+++  
+| VALIDFRAMERATE                           |    1 |   32 |     uint | RO | +++BPM protocol valid frame rate+++ +
-| FRAMESEQ                                 |    1 |   16 | uint |   RO | +++BPM protocol frame sequence+++  
+| INVALIDFRAMERATE                         |    1 |   32 |     uint | RO | +++BPM protocol invalid frame rate+++ +
-| TABLE                                    |  256 |    8 | uint |   RW | +++Packet filter table+++
+| FRAMESEQ                                 |    1 |   16 |     uint | RO | +++BPM protocol frame sequence+++ +
+| FILTERTABLE                              |  256 |   32 | uint | RW | +++BPM filter table+++ +
 |=== 
--- a/hdl/top_combpm_electron.vhd
+++ b/hdl/top_combpm_electron.vhd
@@ -69,6 +69,8 @@ architecture struct of top_combpm_electron is
    signal usrclk             : std_logic;
    signal rst                : std_logic;
+    signal pps_resync         : std_logic;
    signal frame_seq_cnt      : std_logic_vector(15 downto 0);
    signal frame_valid_cnt    : std_logic_vector(31 downto 0);
    signal frame_invalid_cnt  : std_logic_vector(31 downto 0);
@@ -112,6 +114,21 @@ begin
        src_arst => rst_n
    );
+    xpm_cdc_pps_inst: xpm_cdc_pulse
+    generic map (
+        RST_USED => 0,
+        DEST_SYNC_FF => 4,
+        INIT_SYNC_FF => 0
+    )
+    port map (
+        dest_clk    => usrclk,
+        dest_pulse  => pps_resync,
+        src_rst     => '0',
+        dest_rst    => '0',
+        src_clk     => free_100_clk,
+        src_pulse   => pps
+    );
    -- Reset invert polarity
    rst <= not rst_n;
@@ -202,16 +219,16 @@ begin
        addrmap_w.SFP.RXLOS.data(0)                       <= cdc_status_array_axi(0);
        addrmap_w.SFP.MODABS.data(0)                      <= cdc_status_array_axi(1);
-        addrmap_w.GT.POWERGOOD.data(0)              <= cdc_status_array_axi(2);
+        addrmap_w.GT_STATUS.POWERGOOD.data(0)             <= cdc_status_array_axi(2);
-        addrmap_w.GT.QPLLLOCK.data(0)               <= cdc_status_array_axi(3);
+        addrmap_w.GT_STATUS.QPLLLOCK.data(0)              <= cdc_status_array_axi(3);
-        addrmap_w.GT.RXCDRLOCK.data(0)              <= cdc_status_array_axi(4);
+        addrmap_w.GT_STATUS.RXCDRLOCK.data(0)             <= cdc_status_array_axi(4);
-        addrmap_w.GT.RXRESETDONE.data(0)            <= cdc_status_array_axi(5);
+        addrmap_w.GT_STATUS.RXRESETDONE.data(0)           <= cdc_status_array_axi(5);
-        addrmap_w.GT.RXBYTEISALIGNED.data(0)        <= cdc_status_array_axi(6);
+        addrmap_w.GT_STATUS.RXBYTEISALIGNED.data(0)       <= cdc_status_array_axi(6);
-        addrmap_w.GT.RXBYTEREALIGN.data(0)          <= cdc_status_array_axi(7);
+        addrmap_w.GT_STATUS.RXBYTEREALIGN.data(0)         <= cdc_status_array_axi(7);
-        addrmap_w.GT.RXCOMMADET.data(0)             <= cdc_status_array_axi(8);
+        addrmap_w.GT_STATUS.RXCOMMADET.data(0)            <= cdc_status_array_axi(8);
-        addrmap_w.PROTOCOL.FRAMEERROR.data(0)       <= cdc_status_array_axi(9);
+        addrmap_w.PROTOCOL_ERROR.FRAMEERROR.data(0)       <= cdc_status_array_axi(9);
-        addrmap_w.PROTOCOL.SEQFRAMECNTERROR.data(0) <= cdc_status_array_axi(10);
+        addrmap_w.PROTOCOL_ERROR.SEQFRAMECNTERROR.data(0) <= cdc_status_array_axi(10);
-        addrmap_w.PROTOCOL.SEQFRAMEDISCONT.data(0)  <= cdc_status_array_axi(11);
+        addrmap_w.PROTOCOL_ERROR.SEQFRAMEDISCONT.data(0)  <= cdc_status_array_axi(11);
        addrmap_w.VALIDFRAMECNT.data.data                 <= cdc_status_array_axi(43 downto 12);
        addrmap_w.INVALIDFRAMECNT.data.data               <= cdc_status_array_axi(75 downto 44);
@@ -219,9 +236,9 @@ begin
        addrmap_w.INVALIDFRAMERATE.data.data              <= cdc_status_array_axi(139 downto 108);
        addrmap_w.FRAMESEQ.data.data                      <= cdc_status_array_axi(155 downto 140);
-        cdc_control_array_axi(0)                    <= addrmap_r.GT.RXRSTDATAPATH.data(0);
+        cdc_control_array_axi(0)                          <= addrmap_r.GT_CONTROL.RXRSTDATAPATH.data(0);
-        cdc_control_array_axi(1)                    <= addrmap_r.GT.RXRSTPLLDATAPATH.data(0);
+        cdc_control_array_axi(1)                          <= addrmap_r.GT_CONTROL.RXRSTPLLDATAPATH.data(0);
-        cdc_control_array_axi(2)                    <= addrmap_r.GT.RXCOMMADETEN.data(0);
+        cdc_control_array_axi(2)                          <= addrmap_r.GT_CONTROL.RXCOMMADETEN.data(0);
    end block blk_desyrdl;
@@ -232,13 +249,13 @@ begin
    port map(
        rst_n              => sync_resetn,
        clk                => usrclk,
-        pps                => pps,
+        pps                => pps_resync,
        gt_datarx          => gt_datarx,
        m_axis_m2s         => m_axis_decoded_m2s,
        mc_time            => mc_time,
-        soft_reset         => addrmap_w.PROTOCOL.SOFTRESET.data(0),
+        soft_reset         => addrmap_w.RESET.SOFTRESET.data(0),
        frame_seq_cnt      => frame_seq_cnt,
        frame_valid_cnt    => frame_valid_cnt,
        frame_invalid_cnt  => frame_invalid_cnt,
@@ -287,7 +304,7 @@ begin
        -- Status
        gtwiz_userclk_tx_active_out           => open,
-        gtwiz_userclk_rx_active_out           => addrmap_w.GT.RXCLKACTIVE.data,
+        gtwiz_userclk_rx_active_out           => addrmap_w.GT_STATUS.RXCLKACTIVE.data,
        gtwiz_reset_tx_done_out               => open,
        gtwiz_reset_rx_done_out(0)            => gt_rxresetdone,
        gtpowergood_out(0)                    => gt_powergood,

--- a/rdl/combpm.rdl
+++ b/rdl/combpm.rdl
@@ -12,8 +12,7 @@ addrmap combpm {
    reg {
        desc="Module Identification Number";
-        default sw = r;
+        default sw = r; default hw = r;
-        default hw = r;
        field {} data[32] = `C_ID;
    } ID @0x00;
@@ -33,61 +32,41 @@ addrmap combpm {
    } SFP;
    reg {
-        desc="GT transceivers status and control";
+        desc="GT transceivers status";
        desyrdl_data_type="bitfields";
+        default sw = r; default hw = w;
+        field {desc="Powergood signal";} POWERGOOD;
+        field {desc="PLL lock signal";} QPLLLOCK;
+        field {desc="RX clk active signal";} RXCLKACTIVE;
+        field {desc="RX CDR lock signal";} RXCDRLOCK;
+        field {desc="RX reset done signal";} RXRESETDONE;
+        field {desc="RX byte is aligned signal";} RXBYTEISALIGNED;
+        field {desc="RX byte realign signal";} RXBYTEREALIGN;
+        field {desc="RX comma detected signal";} RXCOMMADET;
+    } GT_STATUS;
-        field {desc="Powergood signal";hw=w;sw=r;
+    reg {
-        } POWERGOOD;
+        desc="GT transceivers control";
+        desyrdl_data_type="bitfields";
-        field {desc="PLL lock signal";hw=w;sw=r;
+        default sw = rw; default hw = r;
-        } QPLLLOCK;
+        field {desc="RX comma detection enable signal";} RXCOMMADETEN = 1;
+        field {desc="Reset RX datapath";} RXRSTDATAPATH = 1;
-        field {desc="RX clk active signal";hw=w;sw=r;
+        field {desc="Reset RX PLL and datapath";} RXRSTPLLDATAPATH = 1;
-        } RXCLKACTIVE;
+    } GT_CONTROL;
-        field {desc="RX CDR lock signal";hw=w;sw=r;
-        } RXCDRLOCK;
-        field {desc="RX reset done signal";hw=w;sw=r;
-        } RXRESETDONE;
-        field {desc="RX byte is aligned signal";hw=w;sw=r;
-        } RXBYTEISALIGNED;
-        field {desc="RX byte realign signal";hw=w;sw=r;
-        } RXBYTEREALIGN;
-        field {desc="RX comma detected signal";hw=w;sw=r;
-        } RXCOMMADET;
-        field {desc="RX comma detection enable signal";hw=r;sw=rw;
-        } RXCOMMADETEN = 1;
-        field {desc="Reset RX datapath";hw=r;sw=rw;
-        } RXRSTDATAPATH = 1;
-        field {desc="Reset RX PLL and datapath";hw=r;sw=rw;
-        } RXRSTPLLDATAPATH = 1;
-    } GT;
    reg {
        desc="BPM protocol status and control";
        desyrdl_data_type="bitfields";
+        default sw = r; default hw = w;
+        field {desc="Frame error";} FRAMEERROR;
+        field {desc="Sequence frame count mismatch";} SEQFRAMECNTERROR;
+        field {desc="Sequence frame discontinuity";} SEQFRAMEDISCONT;
+    } PROTOCOL_ERROR;
-        field {desc="Frame error";hw=w;sw=r;
+    reg  {
-        } FRAMEERROR;
+        default sw = rw; default hw = r;
+        field {desc="Soft reset";} SOFTRESET;
-        field {desc="Sequence frame count mismatch";hw=w;sw=r;
+    } RESET;
-        } SEQFRAMECNTERROR;
-        field {desc="Sequence frame discontinuity";hw=w;sw=r;
-        } SEQFRAMEDISCONT;
-        field {desc="Soft reset";hw=r;sw=rw;
-        } SOFTRESET;
-    } PROTOCOL;
    reg {
        desc="BPM protocol valid frame counters";