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BRONES Romain authored* Import sources from Cell Node initial project
BRONES Romain authored* Import sources from Cell Node initial project
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combpm_protocol_electron_ctrl.vhd 11.11 KiB
-- This file was automatically generated with HECTARE
--
-- DO NOT EDIT
--
-- input_filename = combpm_protocol_electron_ctrl.rdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity combpm_protocol_electron_ctrl_axi is
generic(
G_ADDR_W: integer := 8
);
port (
sfp_txfault_i : in std_logic;
sfp_rxlos_i : in std_logic;
sfp_modabs_i : in std_logic;
sfp_txdisable_o : out std_logic;
gt_powergood_i : in std_logic;
gt_qplllock_i : in std_logic;
gt_txclkactive_i : in std_logic;
gt_rxclkactive_i : in std_logic;
gt_rxcdrlock_i : in std_logic;
gt_txresetdone_i : in std_logic;
gt_rxresetdone_i : in std_logic;
gt_rxbyteisaligned_i : in std_logic;
gt_rxbyterealign_i : in std_logic;
gt_rxcommadet_i : in std_logic;
gt_rxcommadeten_o : out std_logic;
gt_rstall_o : out std_logic;
protocol_framecnt_i : in std_logic_vector(15 downto 0);
protocol_frameerror_i : in std_logic;
clk : in std_logic;
reset : in std_logic;
S_AXI_AWADDR : in std_logic_vector(G_ADDR_W-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(32-1 downto 0);
S_AXI_WSTRB : in std_logic_vector(32/8-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(G_ADDR_W-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(32-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end entity;
architecture arch of combpm_protocol_electron_ctrl_axi is
-- address constants
constant C_ADDR_SFP : integer := 0;
constant C_ADDR_GT : integer := 1;
constant C_ADDR_PROTOCOL : integer := 2;
-- field ranges constants
constant C_FIELD_SFP_TXFAULT_MSB : integer := 0; constant C_FIELD_SFP_TXFAULT_LSB : integer := 0;
constant C_FIELD_SFP_RXLOS_MSB : integer := 1;
constant C_FIELD_SFP_RXLOS_LSB : integer := 1;
constant C_FIELD_SFP_MODABS_MSB : integer := 2;
constant C_FIELD_SFP_MODABS_LSB : integer := 2;
constant C_FIELD_SFP_TXDISABLE_MSB : integer := 3;
constant C_FIELD_SFP_TXDISABLE_LSB : integer := 3;
constant C_FIELD_GT_POWERGOOD_MSB : integer := 0;
constant C_FIELD_GT_POWERGOOD_LSB : integer := 0;
constant C_FIELD_GT_QPLLLOCK_MSB : integer := 1;
constant C_FIELD_GT_QPLLLOCK_LSB : integer := 1;
constant C_FIELD_GT_TXCLKACTIVE_MSB : integer := 2;
constant C_FIELD_GT_TXCLKACTIVE_LSB : integer := 2;
constant C_FIELD_GT_RXCLKACTIVE_MSB : integer := 3;
constant C_FIELD_GT_RXCLKACTIVE_LSB : integer := 3;
constant C_FIELD_GT_RXCDRLOCK_MSB : integer := 4;
constant C_FIELD_GT_RXCDRLOCK_LSB : integer := 4;
constant C_FIELD_GT_TXRESETDONE_MSB : integer := 5;
constant C_FIELD_GT_TXRESETDONE_LSB : integer := 5;
constant C_FIELD_GT_RXRESETDONE_MSB : integer := 6;
constant C_FIELD_GT_RXRESETDONE_LSB : integer := 6;
constant C_FIELD_GT_RXBYTEISALIGNED_MSB : integer := 7;
constant C_FIELD_GT_RXBYTEISALIGNED_LSB : integer := 7;
constant C_FIELD_GT_RXBYTEREALIGN_MSB : integer := 8;
constant C_FIELD_GT_RXBYTEREALIGN_LSB : integer := 8;
constant C_FIELD_GT_RXCOMMADET_MSB : integer := 9;
constant C_FIELD_GT_RXCOMMADET_LSB : integer := 9;
constant C_FIELD_GT_RXCOMMADETEN_MSB : integer := 10;
constant C_FIELD_GT_RXCOMMADETEN_LSB : integer := 10;
constant C_FIELD_GT_RSTALL_MSB : integer := 11;
constant C_FIELD_GT_RSTALL_LSB : integer := 11;
constant C_FIELD_PROTOCOL_FRAMECNT_MSB : integer := 15;
constant C_FIELD_PROTOCOL_FRAMECNT_LSB : integer := 0;
constant C_FIELD_PROTOCOL_FRAMEERROR_MSB : integer := 16;
constant C_FIELD_PROTOCOL_FRAMEERROR_LSB : integer := 16;
-- registers
signal reg_sfp : std_logic_vector(32-1 downto 0);
signal reg_gt : std_logic_vector(32-1 downto 0);
signal reg_protocol : std_logic_vector(32-1 downto 0);
-- read
type t_state_read is (sReadIdle, sReadValid);
signal state_read : t_state_read;
signal rdata_reg : std_logic_vector(31 downto 0);
signal raddr_word : integer;
signal arready_wire : std_logic;
signal rvalid_wire : std_logic;
-- write
type t_state_write is (sWriteIdle, sWriteWaitData, sWriteWaitAddr, sWriteResp);
signal state_write : t_state_write;
signal state_write_prev : t_state_write;
signal waddr_reg : std_logic_vector(G_ADDR_W-1 downto 0);
signal wdata_reg : std_logic_vector(31 downto 0);
signal waddr_word : integer;
signal awready_wire : std_logic;
signal wready_wire : std_logic;
signal bvalid_wire : std_logic;
begin
reg_sfp(0) <= sfp_txfault_i when rising_edge(clk); reg_sfp(1) <= sfp_rxlos_i when rising_edge(clk);
reg_sfp(2) <= sfp_modabs_i when rising_edge(clk);
sfp_txdisable_o <= reg_sfp(3);
reg_gt(0) <= gt_powergood_i when rising_edge(clk);
reg_gt(1) <= gt_qplllock_i when rising_edge(clk);
reg_gt(2) <= gt_txclkactive_i when rising_edge(clk);
reg_gt(3) <= gt_rxclkactive_i when rising_edge(clk);
reg_gt(4) <= gt_rxcdrlock_i when rising_edge(clk);
reg_gt(5) <= gt_txresetdone_i when rising_edge(clk);
reg_gt(6) <= gt_rxresetdone_i when rising_edge(clk);
reg_gt(7) <= gt_rxbyteisaligned_i when rising_edge(clk);
reg_gt(8) <= gt_rxbyterealign_i when rising_edge(clk);
reg_gt(9) <= gt_rxcommadet_i when rising_edge(clk);
gt_rxcommadeten_o <= reg_gt(10);
gt_rstall_o <= reg_gt(11);
reg_protocol(15 downto 0) <= protocol_framecnt_i when rising_edge(clk);
reg_protocol(16) <= protocol_frameerror_i when rising_edge(clk);
proc_state_read: process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
state_read <= sReadIdle;
else
case state_read is
when sReadIdle =>
if S_AXI_ARVALID = '1' then
state_read <= sReadValid;
end if;
when sReadValid =>
if S_AXI_RREADY = '1' then
state_read <= sReadIdle;
end if;
end case;
end if;
end if;
end process;
raddr_word <= to_integer(unsigned(S_AXI_ARADDR(G_ADDR_W-1 downto 2)));
-- ### read logic
proc_rdata_reg: process (clk)
begin
if rising_edge(clk) then
rdata_reg <= (others => '0');
case raddr_word is
when C_ADDR_SFP =>
rdata_reg(0 downto 0) <= reg_sfp(0 downto 0);
rdata_reg(1 downto 1) <= reg_sfp(1 downto 1);
rdata_reg(2 downto 2) <= reg_sfp(2 downto 2);
rdata_reg(3 downto 3) <= reg_sfp(3 downto 3);
when C_ADDR_GT =>
rdata_reg(0 downto 0) <= reg_gt(0 downto 0);
rdata_reg(1 downto 1) <= reg_gt(1 downto 1);
rdata_reg(2 downto 2) <= reg_gt(2 downto 2);
rdata_reg(3 downto 3) <= reg_gt(3 downto 3);
rdata_reg(4 downto 4) <= reg_gt(4 downto 4);
rdata_reg(5 downto 5) <= reg_gt(5 downto 5);
rdata_reg(6 downto 6) <= reg_gt(6 downto 6);
rdata_reg(7 downto 7) <= reg_gt(7 downto 7);
rdata_reg(8 downto 8) <= reg_gt(8 downto 8);
rdata_reg(9 downto 9) <= reg_gt(9 downto 9);
rdata_reg(10 downto 10) <= reg_gt(10 downto 10);
rdata_reg(11 downto 11) <= reg_gt(11 downto 11);
when C_ADDR_PROTOCOL =>
rdata_reg(15 downto 0) <= reg_protocol(15 downto 0); rdata_reg(16 downto 16) <= reg_protocol(16 downto 16);
when others =>
-- decode error
rdata_reg <= x"badc0fee";
end case;
end if;
end process;
proc_read_output: process (state_read)
begin
case state_read is
when sReadIdle =>
arready_wire <= '1';
rvalid_wire <= '0';
when sReadValid =>
arready_wire <= '0';
rvalid_wire <= '1';
when others =>
arready_wire <= '0';
rvalid_wire <= '0';
end case;
end process;
S_AXI_ARREADY <= arready_wire;
S_AXI_RVALID <= rvalid_wire;
S_AXI_RDATA <= rdata_reg;
S_AXI_RRESP <= "00";
proc_state_write_prev: process (clk) begin
if rising_edge(clk) then
state_write_prev <= state_write;
end if;
end process;
proc_state_write: process (clk) begin
if rising_edge (clk) then
if reset = '1' then
state_write <= sWriteIdle;
else
case state_write is
when sWriteIdle =>
if S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' then
state_write <= sWriteResp;
waddr_reg <= S_AXI_AWADDR;
wdata_reg <= S_AXI_WDATA;
elsif S_AXI_AWVALID = '1' and S_AXI_WVALID = '0' then
state_write <= sWriteWaitData;
waddr_reg <= S_AXI_AWADDR;
elsif S_AXI_AWVALID = '0' and S_AXI_WVALID = '1' then
state_write <= sWriteWaitAddr;
wdata_reg <= S_AXI_WDATA;
end if;
when sWriteWaitData =>
if S_AXI_WVALID = '1' then
state_write <= sWriteResp;
wdata_reg <= S_AXI_WDATA;
end if;
when sWriteWaitAddr =>
if S_AXI_AWVALID = '1' then
state_write <= sWriteResp;
waddr_reg <= S_AXI_AWADDR;
end if;
when sWriteResp =>
if S_AXI_BREADY = '1' then
state_write <= sWriteIdle;
end if;
end case;
end if;
end if;
end process;
waddr_word <= to_integer(unsigned(waddr_reg(G_ADDR_W-1 downto 2)));
-- ### write logic (use waddr_word and wdata_reg)
proc_write: process (clk) begin
if rising_edge(clk) then
if reset = '1' then
reg_sfp(3 downto 3) <= "0";
reg_gt(10 downto 10) <= "1";
reg_gt(11 downto 11) <= "1";
else
-- default (pulse)
-- default (swmod)
-- default (woclr)
if state_write = sWriteResp and state_write_prev /= sWriteResp then
case waddr_word is
when C_ADDR_SFP =>
reg_sfp(3 downto 3) <= wdata_reg(3 downto 3);
when C_ADDR_GT =>
reg_gt(10 downto 10) <= wdata_reg(10 downto 10);
reg_gt(11 downto 11) <= wdata_reg(11 downto 11);
when C_ADDR_PROTOCOL =>
null;
when others =>
null;
end case;
end if;
end if;
end if;
end process;
proc_write_output: process (state_write) begin
case state_write is
when sWriteIdle =>
awready_wire <= '1';
wready_wire <= '1';
bvalid_wire <= '0';
when sWriteWaitData =>
awready_wire <= '0';
wready_wire <= '1';
bvalid_wire <= '0';
when sWriteWaitAddr =>
awready_wire <= '1';
wready_wire <= '0';
bvalid_wire <= '0';
when sWriteResp =>
awready_wire <= '0';
wready_wire <= '0';
bvalid_wire <= '1';
when others =>
awready_wire <= '0';
wready_wire <= '0';
bvalid_wire <= '0';
end case;
end process;
S_AXI_AWREADY <= awready_wire;
S_AXI_WREADY <= wready_wire;
S_AXI_BRESP <= "00";
S_AXI_BVALID <= bvalid_wire;
end architecture;