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DG
FOFB
fofbnode_fpga
Commits
e10ba1ea
Commit
e10ba1ea
authored
Apr 24, 2024
by
BRONES Romain
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feat: add FIFO for comlbp CDC
* Theorically, this was in the interconnect, without success
parent
6b2f3aa5
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Changes
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2 changed files
src/app_fofbnode/hdl/top_app_cellnode.vhd
+58
-4
58 additions, 4 deletions
src/app_fofbnode/hdl/top_app_cellnode.vhd
src/app_fofbnode/tcl/gen_ip_cellnode.tcl
+1
-1
1 addition, 1 deletion
src/app_fofbnode/tcl/gen_ip_cellnode.tcl
with
59 additions
and
5 deletions
src/app_fofbnode/hdl/top_app_cellnode.vhd
+
58
−
4
View file @
e10ba1ea
...
...
@@ -114,8 +114,13 @@ architecture struct of bsp_fmc2zup_payload is
signal
axis_comlbp_tdata_posy
:
std_logic_vector
(
31
downto
0
);
signal
axis_comlbp_tdata_faseq
:
std_logic_vector
(
15
downto
0
);
signal
axis_comlbp_tdata_bpmid
:
std_logic_vector
(
15
downto
0
);
signal
axis_comlbp_tdata
:
std_logic_vector
(
95
downto
0
);
signal
axis_comlbp_tvalid
:
std_logic
;
signal
axis_comlbp_sync_tready
:
std_logic
;
signal
axis_comlbp_sync_tvalid
:
std_logic
;
signal
axis_comlbp_sync_tdata
:
std_logic_vector
(
95
downto
0
);
-- COMCELLNODE signals
signal
clk_comcellnode
:
std_logic
;
...
...
@@ -452,11 +457,60 @@ begin
--------------------------------
-- UPSTREAM AXIS INTERCONNECT --
--------------------------------
axis_comlbp_tdata
<=
axis_comlbp_tdata_faseq
&
axis_comlbp_tdata_bpmid
&
axis_comlbp_tdata_posy
&
axis_comlbp_tdata_posx
;
inst_upstream_lbp_fifo
:
xpm_fifo_axis
generic
map
(
CLOCKING_MODE
=>
"independent_clock"
,
FIFO_DEPTH
=>
64
,
RD_DATA_COUNT_WIDTH
=>
7
,
WR_DATA_COUNT_WIDTH
=>
7
,
RELATED_CLOCKS
=>
0
,
TDATA_WIDTH
=>
96
)
port
map
(
s_aresetn
=>
pi_payload
.
m_axi4l_reg_areset_n
,
almost_empty_axis
=>
open
,
almost_full_axis
=>
open
,
dbiterr_axis
=>
open
,
sbiterr_axis
=>
open
,
prog_empty_axis
=>
open
,
prog_full_axis
=>
open
,
rd_data_count_axis
=>
open
,
wr_data_count_axis
=>
open
,
injectdbiterr_axis
=>
'0'
,
injectsbiterr_axis
=>
'0'
,
s_aclk
=>
clk_comlbp
,
s_axis_tvalid
=>
axis_comlbp_tvalid
,
s_axis_tdata
=>
axis_comlbp_tdata
,
s_axis_tready
=>
open
,
s_axis_tdest
=>
(
others
=>
'0'
),
s_axis_tid
=>
(
others
=>
'0'
),
s_axis_tkeep
=>
(
others
=>
'0'
),
s_axis_tlast
=>
'0'
,
s_axis_tstrb
=>
(
others
=>
'0'
),
s_axis_tuser
=>
(
others
=>
'0'
),
m_aclk
=>
pi_payload
.
m_axi4l_reg_aclk
,
m_axis_tdata
=>
axis_comlbp_sync_tdata
,
m_axis_tready
=>
axis_comlbp_sync_tready
,
m_axis_tvalid
=>
axis_comlbp_sync_tvalid
--m_axis_tdest => open,
--m_axis_tid => open,
--m_axis_tkeep => open,
--m_axis_tlast => open,
--m_axis_tstrb => open,
--m_axis_tuser => open
);
inst_rx_axis_ic
:
entity
work
.
axis_com51_rx
port
map
(
aclk
=>
pi_payload
.
m_axi4l_reg_aclk
,
s01_axis_aclk
=>
clk_combpm
,
s00_axis_aclk
=>
clk_comlbp
,
s00_axis_aclk
=>
pi_payload
.
m_axi4l_reg_aclk
,
s02_axis_aclk
=>
clk_comlbp
,
s03_axis_aclk
=>
clk_comlbp
,
s04_axis_aclk
=>
clk_comlbp
,
...
...
@@ -474,9 +528,9 @@ begin
s01_axis_tready
=>
open
,
s01_axis_tdata
=>
x"00"
&
axis_combpm_tdata
(
127
downto
120
)
&
axis_combpm_tdata
(
79
downto
0
),
s00_axis_tvalid
=>
axis_comlbp_tvalid
,
s00_axis_tready
=>
open
,
s00_axis_tdata
=>
axis_comlbp_
tdata_faseq
&
axis_comlbp_tdata_bpmid
&
axis_comlbp_tdata_posy
&
axis_comlbp
_tdata
_posx
,
s00_axis_tvalid
=>
axis_comlbp_
sync_
tvalid
,
s00_axis_tready
=>
axis_comlbp_sync_tready
,
s00_axis_tdata
=>
axis_comlbp_
sync
_tdata
,
s02_axis_tvalid
=>
'0'
,
s02_axis_tready
=>
open
,
...
...
This diff is collapsed.
Click to expand it.
src/app_fofbnode/tcl/gen_ip_cellnode.tcl
+
1
−
1
View file @
e10ba1ea
...
...
@@ -25,7 +25,7 @@ set_property -dict [list \
CONFIG.HAS_TUSER
{
false
}
\
CONFIG.SWITCH_TUSER_BITS_PER_BYTE
{
1
}
\
CONFIG.ARBITER_TYPE
{
Fixed
}
\
CONFIG.C_S00_AXIS_IS_ACLK_ASYNC
{
1
}
\
CONFIG.C_S00_AXIS_IS_ACLK_ASYNC
{
0
}
\
CONFIG.C_S01_AXIS_IS_ACLK_ASYNC
{
1
}
\
CONFIG.C_S02_AXIS_IS_ACLK_ASYNC
{
1
}
\
CONFIG.C_S03_AXIS_IS_ACLK_ASYNC
{
1
}
\
...
...
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