wip: increase IC fifo and switch S00 S01

src/app_fofbnode/hdl/top_app_cellnode.vhd

@@ -455,8 +455,8 @@ begin
     inst_rx_axis_ic: entity work.axis_com51_rx
     port map (
         aclk                 => pi_payload.m_axi4l_reg_aclk,
-        s00_axis_aclk        => clk_combpm,
-        s01_axis_aclk        => clk_comlbp,
+        s01_axis_aclk        => clk_combpm,
+        s00_axis_aclk        => clk_comlbp,
         s02_axis_aclk        => clk_comlbp,
         s03_axis_aclk        => clk_comlbp,
         s04_axis_aclk        => clk_comlbp,
@@ -470,13 +470,13 @@ begin
         s04_axis_aresetn     => pi_payload.m_axi4l_reg_areset_n,
         m00_axis_aresetn     => pi_payload.m_axi4l_reg_areset_n,
 
-        s00_axis_tvalid      => axis_combpm_tvalid,
-        s00_axis_tready      => open,
-        s00_axis_tdata       => x"00" & axis_combpm_tdata(127 downto 120) & axis_combpm_tdata(79 downto 0),
-
-        s01_axis_tvalid      => axis_comlbp_tvalid,
+        s01_axis_tvalid      => axis_combpm_tvalid,
         s01_axis_tready      => open,
-        s01_axis_tdata       => axis_comlbp_tdata_faseq & axis_comlbp_tdata_bpmid & axis_comlbp_tdata_posy & axis_comlbp_tdata_posx,
+        s01_axis_tdata       => x"00" & axis_combpm_tdata(127 downto 120) & axis_combpm_tdata(79 downto 0),
+
+        s00_axis_tvalid      => axis_comlbp_tvalid,
+        s00_axis_tready      => open,
+        s00_axis_tdata       => axis_comlbp_tdata_faseq & axis_comlbp_tdata_bpmid & axis_comlbp_tdata_posy & axis_comlbp_tdata_posx,
 
         s02_axis_tvalid      => '0',
         s02_axis_tready      => open,

src/app_fofbnode/tcl/gen_ip_cellnode.tcl

@@ -30,16 +30,18 @@ set_property -dict [list \
     CONFIG.C_S02_AXIS_IS_ACLK_ASYNC {1} \
     CONFIG.C_S03_AXIS_IS_ACLK_ASYNC {1} \
     CONFIG.C_S04_AXIS_IS_ACLK_ASYNC {1} \
+    CONFIG.M00_AXIS_FIFO_MODE {1_(Normal)} \
+    CONFIG.C_M00_AXIS_FIFO_DEPTH {128} \
     CONFIG.S00_AXIS_FIFO_MODE {1_(Normal)} \
-    CONFIG.C_S00_AXIS_FIFO_DEPTH {64} \
+    CONFIG.C_S00_AXIS_FIFO_DEPTH {128} \
     CONFIG.S01_AXIS_FIFO_MODE {1_(Normal)} \
-    CONFIG.C_S01_AXIS_FIFO_DEPTH {64} \
+    CONFIG.C_S01_AXIS_FIFO_DEPTH {128} \
     CONFIG.S02_AXIS_FIFO_MODE {1_(Normal)} \
-    CONFIG.C_S02_AXIS_FIFO_DEPTH {64} \
+    CONFIG.C_S02_AXIS_FIFO_DEPTH {128} \
     CONFIG.S03_AXIS_FIFO_MODE {1_(Normal)} \
-    CONFIG.C_S03_AXIS_FIFO_DEPTH {64} \
+    CONFIG.C_S03_AXIS_FIFO_DEPTH {128} \
     CONFIG.S04_AXIS_FIFO_MODE {1_(Normal)} \
-    CONFIG.C_S04_AXIS_FIFO_DEPTH {64} \
+    CONFIG.C_S04_AXIS_FIFO_DEPTH {128} \
     CONFIG.SWITCH_PACKET_MODE {false} \
     CONFIG.C_SWITCH_MAX_XFERS_PER_ARB {1} \
     CONFIG.C_SWITCH_NUM_CYCLES_TIMEOUT {0} \
@@ -49,6 +51,7 @@ set_property -dict [list \
     CONFIG.S02_AXIS_TDATA_NUM_BYTES {12} \
     CONFIG.S03_AXIS_TDATA_NUM_BYTES {12} \
     CONFIG.S04_AXIS_TDATA_NUM_BYTES {12} \
+    CONFIG.M00_S00_CONNECTIVITY {true} \
     CONFIG.M00_S01_CONNECTIVITY {true} \
     CONFIG.M00_S02_CONNECTIVITY {true} \
     CONFIG.M00_S03_CONNECTIVITY {true} \