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hexapodfmbo

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    COMCORR module documentation

    Description

    This module provides communication with BILT PSU corrector. It uses the CACTUS RTM to sent UART words over RS422 signals.

    The input is an AXIS with correction packets.

    Overview

    Main operation: Top level

    Basic overview of comcorr module

    This module reproduce an identical logic for the 32 line drivers. The AXIS packets are presented to every line input. The PSC ID is check against each line configuration. The correction data is loaded in the UART shift register only if the configuration matches the incoming ID.

    • Rate ticker. Simple counter, configured to send one clock tick every N clocks. Two rates are sent, rate tick is the UART bitrate, period tick start the reloading/sending of a word.

    • Shift register. Shift bits on each tick. The register is loaded when load='1'. The input data bits are distributed in the register, along with the parity, start and stop signaling. The register is 22 symbol bits total. Bits are shifted out at each rate ticker, and a logic '1' is loaded in the register, thus the line hangs at level high when the word is fully sent.

    • PSC ID check. Simple bit by bit comparator.

    Package

    A package describing the AXIS packet at the module input is included. It helps to automatically pack or unpack the packet (functions corrpacket2slv() or slv2corrpacket() ). A zero packet (C_CORRPACKET_ZERO) is also declared.

    Table 1. t_corrpacket record type
    Member name Type Description

    psc_id

    std_logic_vector(15 downto 0)

    ID of the Power Supply Corrector.

    corr_val

    std_logic_vector(31 downto 0)

    Correction value.

    Some usage of pkg_corrpacket.vhd
        signal my_packet    : t_corrpacket;
    
    (...)
    
        my_packet  <= slv2corrpacket(axis_tdata);  -- Convert from AXIS tdata to a corr packet
    
        id      <= my_packet.psu_id;             -- Access packet fields
        pos_x   <= my_packet.corr_val;
    
        axis_tdata_o <= corrpacket2slv(my_packet); -- Convert back to logic vector for AXIS tdata

    Details

    Structural schematic of comcorr

    On the shift register, the load_value is loaded when load is high. Parity bits are integrated to the value. Bits are shifted out at every rate tick.

    Rate divider

    The divider value to set are the number of the main clock period to count. For example a UART rate divider of 80 and a main clock at 100MHz set a UART bitrate at 1.25 Mbps.

    Setting a period rate divider to 0 allows direct sending of the word. The AXIS rate gives the word rate.

    Registers map

    Table 2. Register
    Name N bits type RW Description

    VERSION

    1

    32

    uint

    RO

    Module version

    CONFIG

    1

    1

    uint

    RW

    Configuration register

    RATEDIV

    1

    32

    uint

    RW

    Rate divider for UART

    PERIOD

    1

    32

    uint

    RW

    Rate divider for Period

    bld_arr

    32

    17

    uint

    RW

    BILT line driver configuration register
    - PSCID [15:0] sw:RW uint : PSC ID for this line driver
    - ENA [16:16] sw:RW uint : Enable the line driver

    TODO/Future of this module

    • Remove the record on the top level (and in the package) and use directly named signals. ie s_axis_tdata_pscid

    • Better integration to FWK/GHDL