COMCORR module documentation
Description
This module provides communication with BILT PSU corrector. It uses the CACTUS RTM to sent UART words over RS422 signals.
The input is an AXIS with correction packets.
Overview
Main operation: Top level
This module reproduce an identical logic for the 32 line drivers. The AXIS packets are presented to every line input. The PSC ID is check against each line configuration. The correction data is loaded in the UART shift register only if the configuration matches the incoming ID.
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Rate ticker. Simple counter, configured to send one clock tick every N clocks. Two rates are sent, rate tick is the UART bitrate, period tick start the reloading/sending of a word.
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Shift register. Shift bits on each tick. The register is loaded when load='1'. The input data bits are distributed in the register, along with the parity, start and stop signaling. The register is 22 symbol bits total. Bits are shifted out at each rate ticker, and a logic '1' is loaded in the register, thus the line hangs at level high when the word is fully sent.
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PSC ID check. Simple bit by bit comparator.
Package
A package describing the AXIS packet at the module input is included. It helps to automatically pack or unpack the packet (functions corrpacket2slv() or slv2corrpacket() ). A zero packet (C_CORRPACKET_ZERO) is also declared.
Member name | Type | Description |
---|---|---|
psc_id |
std_logic_vector(15 downto 0) |
ID of the Power Supply Corrector. |
corr_val |
std_logic_vector(31 downto 0) |
Correction value. |
signal my_packet : t_corrpacket;
(...)
my_packet <= slv2corrpacket(axis_tdata); -- Convert from AXIS tdata to a corr packet
id <= my_packet.psu_id; -- Access packet fields
pos_x <= my_packet.corr_val;
axis_tdata_o <= corrpacket2slv(my_packet); -- Convert back to logic vector for AXIS tdata
Details
On the shift register, the load_value is loaded when load is high. Parity bits are integrated to the value. Bits are shifted out at every rate tick.
Registers map
Name | N | bits | type | RW | Description |
---|---|---|---|---|---|
VERSION |
1 |
32 |
uint |
RO |
Module version |
CONFIG |
1 |
1 |
uint |
RW |
Configuration register |
RATEDIV |
1 |
32 |
uint |
RW |
Rate divider for UART |
PERIOD |
1 |
32 |
uint |
RW |
Rate divider for Period |
bld_arr |
32 |
17 |
uint |
RW |
BILT line driver configuration register |