feat:Increas phase maximum width

* Separate phase offset (and reset) and incr in two memories
* This allows a phase increment up to 32 bits and a phase offset up to
  31 bits

hdl/MultiPhaseTable.vhd

@@ -13,11 +13,16 @@ entity MultiPhaseTable is
         rstn    : in std_logic;
 
         -- Memory map to table
-        pi_table_en         : in std_logic;
-        pi_table_we         : in std_logic;
-        pi_table_addr       : in std_logic_vector(C_W_TIDX-1 downto 0);
-        pi_table_data       : in std_logic_vector(2*C_W_PHASE downto 0);
-        po_table_data       : out std_logic_vector(2*C_W_PHASE downto 0);
+        pi_table_incr_en         : in std_logic;
+        pi_table_incr_we         : in std_logic;
+        pi_table_incr_addr       : in std_logic_vector(C_W_TIDX-1 downto 0);
+        pi_table_incr_data       : in std_logic_vector(C_W_PHASE-1 downto 0);
+        po_table_incr_data       : out std_logic_vector(C_W_PHASE-1 downto 0);
+        pi_table_offs_en         : in std_logic;
+        pi_table_offs_we         : in std_logic;
+        pi_table_offs_addr       : in std_logic_vector(C_W_TIDX-1 downto 0);
+        pi_table_offs_data       : in std_logic_vector(C_W_PHASE downto 0);
+        po_table_offs_data       : out std_logic_vector(C_W_PHASE downto 0);
 
         -- Configuration
         ticker_enable       : in std_logic;
@@ -48,7 +53,8 @@ architecture rtl of MultiPhaseTable is
     signal r_phase_tidx    : std_logic_vector(C_W_TIDX-1 downto 0);
     signal r_phase_valid   : std_logic;
 
-    signal table_data      : std_logic_vector(C_W_PHASE*2 downto 0); -- offset, incr and reset
+    signal table_incr_data      : std_logic_vector(C_W_PHASE-1 downto 0);
+    signal table_offs_data      : std_logic_vector(C_W_PHASE downto 0);
 
 begin
 
@@ -101,36 +107,61 @@ begin
     tidx <= std_logic_vector(tidx_cnt);
 
 
-    -----------------
-    -- PHASE TABLE --
-    -----------------
+    ----------------------
+    -- PHASE INCR TABLE --
+    ----------------------
     -- Port A is read write from AXI controller, Port B is read only from logic
-    inst_phase_table: entity desy.ram_tdp
+    inst_incr_table: entity desy.ram_tdp
     generic map(
         G_ADDR  => C_W_TIDX,
-        G_DATA  => 2*C_W_PHASE+1
+        G_DATA  => C_W_PHASE
     )
     port map(
         pi_clk_a    => clk,
-        pi_en_a     => pi_table_en,
-        pi_we_a     => pi_table_we,
-        pi_addr_a   => pi_table_addr,
-        pi_data_a   => pi_table_data,
-        po_data_a   => po_table_data,
+        pi_en_a     => pi_table_incr_en,
+        pi_we_a     => pi_table_incr_we,
+        pi_addr_a   => pi_table_incr_addr,
+        pi_data_a   => pi_table_incr_data,
+        po_data_a   => po_table_incr_data,
         pi_clk_b    => clk,
         pi_en_b     => '1',
         pi_we_b     => '0',
         pi_addr_b   => std_logic_vector(tidx),
         pi_data_b   => (others => '0'),
-        po_data_b   => table_data
+        po_data_b   => table_incr_data
     );
     -- Unpack phase data
-    po_phase_reset  <= table_data(2*C_W_PHASE);
-    po_phase_offset <= table_data(2*C_W_PHASE-1 downto C_W_PHASE);
-    po_phase_incr   <= table_data(C_W_PHASE-1 downto 0);
+    po_phase_incr   <= table_incr_data(C_W_PHASE-1 downto 0);
     po_phase_valid  <= r_phase_valid;
     po_phase_tidx   <= r_phase_tidx;
 
+    ----------------------
+    -- PHASE OFFS TABLE --
+    ----------------------
+    -- Port A is read write from AXI controller, Port B is read only from logic
+    inst_offs_table: entity desy.ram_tdp
+    generic map(
+        G_ADDR  => C_W_TIDX,
+        G_DATA  => C_W_PHASE+1
+    )
+    port map(
+        pi_clk_a    => clk,
+        pi_en_a     => pi_table_offs_en,
+        pi_we_a     => pi_table_offs_we,
+        pi_addr_a   => pi_table_offs_addr,
+        pi_data_a   => pi_table_offs_data,
+        po_data_a   => po_table_offs_data,
+        pi_clk_b    => clk,
+        pi_en_b     => '1',
+        pi_we_b     => '0',
+        pi_addr_b   => std_logic_vector(tidx),
+        pi_data_b   => (others => '0'),
+        po_data_b   => table_offs_data
+    );
+    -- Unpack offs data
+    po_phase_reset  <= table_offs_data(C_W_PHASE);
+    po_phase_offset <= table_offs_data(C_W_PHASE-1 downto 0);
+
     ------------------------
     -- PIPELINE DELAY REG --
     ------------------------

hdl/top_pscgen.vhd

@@ -83,11 +83,16 @@ begin
         rstn                   => rstn,
 
         -- Memory map to table
-        pi_table_en            => addr_o.table_phase.en,
-        pi_table_we            => addr_o.table_phase.we,
-        pi_table_addr          => addr_o.table_phase.addr(C_W_TIDX-1 downto 0),
-        pi_table_data          => addr_o.table_phase.data,
-        po_table_data          => addr_i.table_phase.data,
+        pi_table_incr_en            => addr_o.table_phase_incr.en,
+        pi_table_incr_we            => addr_o.table_phase_incr.we,
+        pi_table_incr_addr          => addr_o.table_phase_incr.addr(C_W_TIDX-1 downto 0),
+        pi_table_incr_data          => addr_o.table_phase_incr.data,
+        po_table_incr_data          => addr_i.table_phase_incr.data,
+        pi_table_offs_en            => addr_o.table_phase_offs.en,
+        pi_table_offs_we            => addr_o.table_phase_offs.we,
+        pi_table_offs_addr          => addr_o.table_phase_offs.addr(C_W_TIDX-1 downto 0),
+        pi_table_offs_data          => addr_o.table_phase_offs.data,
+        po_table_offs_data          => addr_i.table_phase_offs.data,
 
         -- Configuration
         ticker_enable          => addr_o.control.enable.data(0),

rdl/pscgen.rdl

@@ -48,10 +48,17 @@ addrmap pscgen {
   } TABLE_DEPTH ;
 
   external mem {
-    desc = "Phase increment and offset table";
-    memwidth = 2*`C_W_PHASE+1;
+    desc = "Phase increment table";
+    memwidth = `C_W_PHASE;
     mementries = 2**`C_W_TIDX;
-  } TABLE_PHASE;
+  } TABLE_PHASE_INCR;
+
+
+  external mem {
+    desc = "Phase offset and reset table";
+    memwidth = `C_W_PHASE+1;
+    mementries = 2**`C_W_TIDX;
+  } TABLE_PHASE_OFFS;
 
   external mem {
     desc = "Signal scale and offset table";

sim/tb_pscgen.vhd

@@ -127,12 +127,17 @@ begin
         for I in 0 to 6 loop
             v_phase_incr := std_logic_vector(to_unsigned(1300*(I+1), C_W_PHASE));
             v_phase_offs := std_logic_vector(to_unsigned(3300*2*I, C_W_PHASE));
+
             v_axi4l_data := (others => '0');
             v_axi4l_data(C_W_PHASE-1 downto 0)  := v_phase_incr;
-            v_axi4l_data(2*C_W_PHASE-1 downto C_W_PHASE)    := v_phase_offs;
-            v_axi4l_data(2*C_W_PHASE)                       := '1'; -- At first reset all
             write_axi4l(std_logic_vector(C_MEM_INFO(0).address+to_unsigned(I*4, C_AXI4L_ADDR_WIDTH)),
                         v_axi4l_data);
+
+            v_axi4l_data := (others => '0');
+            v_axi4l_data(C_W_PHASE-1 downto 0)  := v_phase_offs;
+            v_axi4l_data(C_W_PHASE)             := '1'; -- At first reset all
+            write_axi4l(std_logic_vector(C_MEM_INFO(1).address+to_unsigned(I*4, C_AXI4L_ADDR_WIDTH)),
+                        v_axi4l_data);
         end loop;
 
         -- Scaler table parameters
@@ -142,7 +147,7 @@ begin
             v_axi4l_data := (others => '0');
             v_axi4l_data(C_W_SCALE-1 downto 0)                      := v_scale;
             v_axi4l_data(C_W_OFFSET+C_W_SCALE-1 downto C_W_SCALE)   := v_offset;
-            write_axi4l(std_logic_vector(C_MEM_INFO(1).address+to_unsigned(I*4, C_AXI4L_ADDR_WIDTH)),
+            write_axi4l(std_logic_vector(C_MEM_INFO(2).address+to_unsigned(I*4, C_AXI4L_ADDR_WIDTH)),
                         v_axi4l_data);
         end loop;
 
@@ -158,14 +163,14 @@ begin
 
         -- Phase table parameters
         for I in 0 to 6 loop
-            v_phase_incr := std_logic_vector(to_unsigned(13*(I+1), C_W_PHASE));
-            v_phase_offs := std_logic_vector(to_unsigned(33*I, C_W_PHASE));
+            v_phase_offs := std_logic_vector(to_unsigned(33*2*I, C_W_PHASE));
+
             v_axi4l_data := (others => '0');
-            v_axi4l_data(C_W_PHASE-1 downto 0)              := v_phase_incr;
-            v_axi4l_data(2*C_W_PHASE-1 downto C_W_PHASE)    := v_phase_offs;
-            v_axi4l_data(2*C_W_PHASE)                       := '0'; -- At first reset all
-            write_axi4l(std_logic_vector(C_MEM_INFO(0).address+to_unsigned(I*4, C_AXI4L_ADDR_WIDTH)),
+            v_axi4l_data(C_W_PHASE-1 downto 0)  := v_phase_offs;
+            v_axi4l_data(C_W_PHASE)             := '0';
+            write_axi4l(std_logic_vector(C_MEM_INFO(1).address+to_unsigned(I*4, C_AXI4L_ADDR_WIDTH)),
                         v_axi4l_data);
+
         end loop;
 
         -- infinite wait at the end