Merge branch 'seqnb'

add sequence number to psc_gen

hdl/MultiPhaseTable.vhd

@@ -38,7 +38,9 @@ entity MultiPhaseTable is
         po_phase_offset        : out std_logic_vector(C_W_PHASE-1 downto 0);
         po_phase_reset         : out std_logic;
         po_phase_tidx          : out std_logic_vector(C_W_TIDX-1 downto 0);
-        po_phase_valid         : out std_logic
+        po_phase_valid         : out std_logic;
+
+        seq_inc_out            : out std_logic_vector(7 downto 0)
 
     );
 end entity MultiPhaseTable;
@@ -64,12 +66,14 @@ architecture rtl of MultiPhaseTable is
     signal table_incr_data      : std_logic_vector(C_W_PHASE-1 downto 0);
     signal table_offs_data      : std_logic_vector(C_W_PHASE downto 0);
 
+    signal seq_inc_out_s        : std_logic_vector(7 downto 0);
 begin
 
 
     ---------------------------
     -- TICKER RATE DECOUNTER --
     ---------------------------
+    seq_inc_out <= seq_inc_out_s;
     p_ticker:process(clk, rstn)
     begin
         if rstn = '0' then
@@ -79,9 +83,15 @@ begin
             if ticker_cnt = 0 then
                 ticker_cnt <= unsigned(ticker_rate);
                 ticker_tick <= ticker_enable;
+                if seq_inc_out_s = 255 then 
+                    seq_inc_out_s <= (others => '0');
+                else 
+                    seq_inc_out_s <= seq_inc_out_s + 1;
+                end if;
             else
                 ticker_cnt <= ticker_cnt-1;
                 ticker_tick <= '0';
+
             end if;
         end if;
     end process p_ticker;

hdl/top_pscgen.vhd

@@ -72,6 +72,9 @@ architecture struct of top_pscgen is
 
     signal data_delay       : aslv;
 
+    signal seq_inc_out_s    : std_logic_vector(7 downto 0);
+    signal ticker_enable_s  : std_logic;
+
 begin
 
     rst <= not rstn;
@@ -125,13 +128,15 @@ begin
         po_phase_offset        => phase_offset,
         po_phase_reset         => phase_reset,
         po_phase_tidx          => phase_incr_tidx,
-        po_phase_valid         => phase_incr_valid
+        po_phase_valid         => phase_incr_valid,
+
+        seq_inc_out            => seq_inc_out_s
 
     );
 
     addr_i.table_phase_incr.data(31 downto C_W_PHASE)   <= (others => '0');
     addr_i.table_phase_offs.data(31 downto C_W_PHASE+1) <= (others => '0');
-
+    ticker_enable_s <= addr_o.addr_o.control.enable_ticker.data(0);
     ----------------
     -- PHASE ACCU --
     ----------------
@@ -204,6 +209,7 @@ begin
         po_wave                => wave,
         po_wave_tidx           => wave_tidx,
         po_wave_valid          => wave_valid
+        
     );
 
     gen_fixmsb:if C_W_SCALE+C_W_OFFSET < 32 generate
@@ -243,7 +249,13 @@ begin
                                             signed(wave)
                                         ));
 
+            
+            if ticker_enable_s = '1' then
+                m_axis_tuser <= seq_inc_out_s;
+            else
                 m_axis_tuser  <= data_delay(C_DELAY-1)(G_W_TUSER+C_W_VALUE-1 downto C_W_VALUE);
+            end if;
+
             m_axis_tvalid <= wave_valid;
         end if;
     end process;