fix:Phase width cannot be >16

* This is the max in the DDS.
* TODO: accept accumulator with more width, and crop before DDS.

hdl/pkg_pscgen.vhd

 package pkg_pscgen is
 
-    constant C_W_PHASE   : natural := 20;
+    constant C_W_PHASE   : natural := 16;
     constant C_W_TIDX    : natural := 8;
     constant C_W_SINE    : natural := 26;
     constant C_W_SIG     : natural := 16;