resolve merge

hdl/MultiPhaseTable.vhd

@@ -80,15 +80,12 @@ begin
         if rstn = '0' then
             ticker_cnt      <= (others => '0');
             ticker_tick     <= '0';
+            seq_inc_out_s   <= (others => '0');
         elsif rising_edge(clk) then
             if ticker_cnt = 0 then
                 ticker_cnt <= unsigned(ticker_rate);
                 ticker_tick <= ticker_enable;
-                if seq_inc_out_s = 255 then 
-                    seq_inc_out_s <= (others => '0');
-                else 
                 seq_inc_out_s <= seq_inc_out_s+1;
-                end if;
             else
                 ticker_cnt <= ticker_cnt-1;
                 ticker_tick <= '0';

hdl/top_pscgen.vhd

@@ -213,7 +213,7 @@ begin
     );
 
     gen_fixmsb:if C_W_SCALE+C_W_OFFSET < 32 generate
-        addr_i.table_scale.data(31 downto C_W_SCALE+C_W_OFFSET-1) <= (others => '0');
+        addr_i.table_scale.data(31 downto C_W_SCALE+C_W_OFFSET) <= (others => '0');
     end generate;
 
 
@@ -244,16 +244,20 @@ begin
         elsif rising_edge(clk) then
             m_axis_tdata_pscid          <= wave_tidx;
 
-            m_axis_tdata_value          <= std_logic_vector(f_sum_sat(
-                                            signed(data_delay(C_DELAY-1)(C_W_VALUE-1 downto 0)),
-                                            signed(wave)
-                                        ));
-
 
             if ticker_enable_s = '1' then
                 m_axis_tuser <= seq_inc_out_s;
+
+                m_axis_tdata_value          <= std_logic_vector(wave);
+
             else
                 m_axis_tuser  <= data_delay(C_DELAY-1)(G_W_TUSER+C_W_VALUE-1 downto C_W_VALUE);
+
+                m_axis_tdata_value          <= std_logic_vector(f_sum_sat(
+                                                signed(data_delay(C_DELAY-1)(C_W_VALUE-1 downto 0)),
+                                                signed(wave)
+                                            ));
+
             end if;
 
             m_axis_tvalid <= wave_valid;

sim/tb_pscgen.vhd

@@ -133,9 +133,9 @@ begin
         wait until rising_edge(tb_clk);
 
         -- Write config throught axi4
-        write_axi4l(std_logic_vector(C_REGISTER_INFO(C_TICKER_RATE_ID).address),
+        write_axi4l(std_logic_vector(to_unsigned(16#0C#, C_AXI4L_ADDR_WIDTH)),
                     std_logic_vector(to_unsigned(100, C_AXI4L_DATA_WIDTH)));
-        write_axi4l(std_logic_vector(C_REGISTER_INFO(C_TABLE_DEPTH_ID).address),
+        write_axi4l(std_logic_vector(to_unsigned(16#10#, C_AXI4L_ADDR_WIDTH)),
                     std_logic_vector(to_unsigned(6, C_AXI4L_DATA_WIDTH)));
 
         -- Phase table parameters
@@ -145,13 +145,13 @@ begin
 
             v_axi4l_data := (others => '0');
             v_axi4l_data(C_W_PHASE-1 downto 0)  := v_phase_incr;
-            write_axi4l(std_logic_vector(C_MEM_INFO(0).address+to_unsigned(I*4, C_AXI4L_ADDR_WIDTH)),
+            write_axi4l(std_logic_vector(to_unsigned(16#400# + I*4, C_AXI4L_ADDR_WIDTH)),
                         v_axi4l_data);
 
             v_axi4l_data := (others => '0');
             v_axi4l_data(C_W_PHASE-1 downto 0)  := v_phase_offs;
             v_axi4l_data(C_W_PHASE)             := '1'; -- At first reset all
-            write_axi4l(std_logic_vector(C_MEM_INFO(1).address+to_unsigned(I*4, C_AXI4L_ADDR_WIDTH)),
+            write_axi4l(std_logic_vector(to_unsigned(16#800# + I*4, C_AXI4L_ADDR_WIDTH)),
                         v_axi4l_data);
         end loop;
 
@@ -162,14 +162,14 @@ begin
             v_axi4l_data := (others => '0');
             v_axi4l_data(C_W_SCALE-1 downto 0)                      := v_scale;
             v_axi4l_data(C_W_OFFSET+C_W_SCALE-1 downto C_W_SCALE)   := v_offset;
-            write_axi4l(std_logic_vector(C_MEM_INFO(2).address+to_unsigned(I*4, C_AXI4L_ADDR_WIDTH)),
+            write_axi4l(std_logic_vector(to_unsigned(16#C00# + I*4, C_AXI4L_ADDR_WIDTH)),
                         v_axi4l_data);
         end loop;
 
 
         -- Start the phase accu
         v_axi4l_data := (0=> '1', others => '0');
-        write_axi4l(std_logic_vector(C_REGISTER_INFO(C_CONTROL_ID).address),
+        write_axi4l(std_logic_vector(to_unsigned(16#08#, C_AXI4L_ADDR_WIDTH)),
                     v_axi4l_data);
 
         -- Wait a few iterations, for the accu table to reset
@@ -183,7 +183,7 @@ begin
             v_axi4l_data := (others => '0');
             v_axi4l_data(C_W_PHASE-1 downto 0)  := v_phase_offs;
             v_axi4l_data(C_W_PHASE)             := '0';
-            write_axi4l(std_logic_vector(C_MEM_INFO(1).address+to_unsigned(I*4, C_AXI4L_ADDR_WIDTH)),
+            write_axi4l(std_logic_vector(to_unsigned(16#800# + I*4, C_AXI4L_ADDR_WIDTH)),
                         v_axi4l_data);
 
         end loop;
@@ -194,7 +194,7 @@ begin
         -- ====================================================================================================
         -- Test with INPUT
         v_axi4l_data := (1=> '1', others => '0');
-        write_axi4l(std_logic_vector(C_REGISTER_INFO(C_CONTROL_ID).address),
+        write_axi4l(std_logic_vector(to_unsigned(16#08#, C_AXI4L_ADDR_WIDTH)),
                     v_axi4l_data);
 
         -- Scaler table parameters
@@ -204,13 +204,13 @@ begin
             v_axi4l_data := (others => '0');
             v_axi4l_data(C_W_SCALE-1 downto 0)                      := v_scale;
             v_axi4l_data(C_W_OFFSET+C_W_SCALE-1 downto C_W_SCALE)   := v_offset;
-            write_axi4l(std_logic_vector(C_MEM_INFO(2).address+to_unsigned(I*4, C_AXI4L_ADDR_WIDTH)),
+            write_axi4l(std_logic_vector(to_unsigned(16#C00# + I*4, C_AXI4L_ADDR_WIDTH)),
                         v_axi4l_data);
         end loop;
 
         v_offset := std_logic_vector(to_signed(66, C_W_OFFSET));
         v_axi4l_data(C_W_OFFSET+C_W_SCALE-1 downto C_W_SCALE)   := v_offset;
-        write_axi4l(std_logic_vector(C_MEM_INFO(2).address+to_unsigned(20*4, C_AXI4L_ADDR_WIDTH)),
+        write_axi4l(std_logic_vector(to_unsigned(16#C00# + 20*4, C_AXI4L_ADDR_WIDTH)),
                         v_axi4l_data);
 
         -- Phase table parameters
@@ -220,7 +220,7 @@ begin
             v_axi4l_data := (others => '0');
             v_axi4l_data(C_W_PHASE-1 downto 0)  := v_phase_offs;
             v_axi4l_data(C_W_PHASE)             := '1'; -- At first reset all
-            write_axi4l(std_logic_vector(C_MEM_INFO(1).address+to_unsigned(I*4, C_AXI4L_ADDR_WIDTH)),
+            write_axi4l(std_logic_vector(to_unsigned(16#800# + I*4, C_AXI4L_ADDR_WIDTH)),
                         v_axi4l_data);
         end loop;