Fix: Phase and Table alignement

* For now, phase cannot be >16 bits
* Tables are now well aligned

hdl/pkg_pscgen.vhd

 package pkg_pscgen is
 
-    constant C_W_PHASE   : natural := 20;
+    constant C_W_PHASE   : natural := 16;
     constant C_W_TIDX    : natural := 8;
     constant C_W_SINE    : natural := 26;
     constant C_W_SIG     : natural := 16;

hdl/top_pscgen.vhd

@@ -86,13 +86,13 @@ begin
         pi_table_incr_en            => addr_o.table_phase_incr.en,
         pi_table_incr_we            => addr_o.table_phase_incr.we,
         pi_table_incr_addr          => addr_o.table_phase_incr.addr(C_W_TIDX-1 downto 0),
-        pi_table_incr_data          => addr_o.table_phase_incr.data,
-        po_table_incr_data          => addr_i.table_phase_incr.data,
+        pi_table_incr_data          => addr_o.table_phase_incr.data(C_W_PHASE-1 downto 0),
+        po_table_incr_data          => addr_i.table_phase_incr.data(C_W_PHASE-1 downto 0),
         pi_table_offs_en            => addr_o.table_phase_offs.en,
         pi_table_offs_we            => addr_o.table_phase_offs.we,
         pi_table_offs_addr          => addr_o.table_phase_offs.addr(C_W_TIDX-1 downto 0),
-        pi_table_offs_data          => addr_o.table_phase_offs.data,
-        po_table_offs_data          => addr_i.table_phase_offs.data,
+        pi_table_offs_data          => addr_o.table_phase_offs.data(C_W_PHASE downto 0),
+        po_table_offs_data          => addr_i.table_phase_offs.data(C_W_PHASE downto 0),
 
         -- Configuration
         ticker_enable          => addr_o.control.enable.data(0),
@@ -107,6 +107,9 @@ begin
 
     );
 
+    addr_i.table_phase_incr.data(31 downto C_W_PHASE)   <= (others => '0');
+    addr_i.table_phase_offs.data(31 downto C_W_PHASE+1) <= (others => '0');
+
     ----------------
     -- PHASE ACCU --
     ----------------
@@ -137,7 +140,6 @@ begin
         aclk                                                 => clk,
         aresetn                                              => rstn,
         s_axis_phase_tvalid => '1', -- otherwise DDS get stuck...
-        s_axis_phase_tdata(C_W_EXT_PHASE-1 downto C_W_PHASE) => (others => '0'), -- unused
         s_axis_phase_tdata(C_W_PHASE-1 downto 0)             => phase,
         s_axis_phase_tuser                                   => phase_tidx,
         m_axis_data_tvalid                                   => sine_valid,
@@ -168,8 +170,8 @@ begin
         pi_table_en            => addr_o.table_scale.en,
         pi_table_we            => addr_o.table_scale.we,
         pi_table_addr          => addr_o.table_scale.addr(C_W_TIDX-1 downto 0),
-        pi_table_data          => addr_o.table_scale.data,
-        po_table_data          => addr_i.table_scale.data,
+        pi_table_data          => addr_o.table_scale.data(C_W_SCALE+C_W_OFFSET-1 downto 0),
+        po_table_data          => addr_i.table_scale.data(C_W_SCALE+C_W_OFFSET-1 downto 0),
 
         -- Sine in
         pi_sine                => sine(C_W_SINE-1 downto 0),
@@ -182,6 +184,9 @@ begin
         po_wave_valid          => wave_valid
     );
 
+    gen_fixmsb:if C_W_SCALE+C_W_OFFSET < 32 generate
+        addr_i.table_scale.data(31 downto C_W_SCALE+C_W_OFFSET-1) <= (others => '0');
+    end generate;
 
     ------------------
     -- TIDX MAPPING --

rdl/pscgen.rdl

@@ -49,20 +49,20 @@ addrmap pscgen {
 
   external mem {
     desc = "Phase increment table";
-    memwidth = `C_W_PHASE;
+    memwidth = 32;
     mementries = 2**`C_W_TIDX;
   } TABLE_PHASE_INCR;
 
 
   external mem {
     desc = "Phase offset and reset table";
-    memwidth = `C_W_PHASE+1;
+    memwidth = 32;
     mementries = 2**`C_W_TIDX;
   } TABLE_PHASE_OFFS;
 
   external mem {
     desc = "Signal scale and offset table";
-    memwidth = `C_W_SCALE+`C_W_OFFSET;
+    memwidth = 32;
     mementries = 2**`C_W_TIDX;
   } TABLE_SCALE;
 

tcl/main.tcl

@@ -45,11 +45,9 @@ proc setAddressSpace {} {
 
 # ==============================================================================
 proc doOnCreate {} {
-  variable Vhdl
+  variable Sources
   variable Config
 
-  addSources Vhdl
-
   addSources "Sources"
 
   # Generate Xilinx IPs