Merge branch 'dev_stoptocurrent' into dev

* Port Integrate and Dump to corr_iir

hdl/corr_iir.vhd

@@ -41,6 +41,7 @@ end entity corr_iir;
 
 architecture rtl of corr_iir is
 
+    constant C_INT      : natural := 10;
     constant C_DELAY    : natural := 6;
 
     constant C_W_MULT   : natural := C_W_MM+C_W_COR_COEF;
@@ -106,6 +107,10 @@ begin
         signal enable_corr  : std_logic;
         signal reset_corr   : std_logic;
 
+        signal integrate_dout   : signed(C_W_COR+C_INT-1 downto 0);
+        signal avg_dout         : signed(C_W_COR-1 downto 0);
+        signal integrate_cnt    : unsigned(C_INT-1 downto 0);
+
     begin
 
         -- Signal rails for X/Y coef and enable/reset, based on PSCID number
@@ -142,6 +147,9 @@ begin
                 rndsat_mult_a   <= (others => '0');
                 rndsat_mult_b   <= (others => '0');
                 rndsat_mult_d   <= (others => '0');
+                integrate_dout  <= (others => '0');
+                integrate_cnt   <= (others => '0');
+                avg_dout        <= (others => '0');
             elsif rising_edge(clk) then
 
                 ----------------------------------------------------------------------------------------------------------
@@ -149,12 +157,17 @@ begin
                 if reset_corr = '1' then
                     reg_din         <= (others => '0');
                     reg_dout        <= (others => '0');
+                    integrate_dout  <= (others => '0');
+                    integrate_cnt   <= (others => '0');
+                    avg_dout        <= (others => '0');
                 else
                     if matmult_valid = '1' then
                         reg_din     <= matmult(I);
                     end if;
 
-                    if delay_valid(delay_valid'left-2) = '1' and enable_corr = '1' then
+                    if enable_corr = '1' then
+
+                        if delay_valid(delay_valid'left-2) = '1' then
 
                             -- Round then sat
                             if mult_c(C_W_COR_COEFFP-1) = '0' then
@@ -167,6 +180,19 @@ begin
                                             C_W_CORFP);
                             end if;
                         end if;
+
+                        if delay_valid(delay_valid'left) = '1' then
+                            integrate_cnt   <= integrate_cnt-1;
+                            if integrate_cnt = 0 then
+                                avg_dout        <= integrate_dout(C_W_COR+C_INT-1 downto C_INT);
+                                integrate_dout  <= (others => '0');
+                            else
+                                integrate_dout  <= integrate_dout+rnd_cor;
+                            end if;
+                        end if;
+
+                    end if;
+
                 end if;
 
                 ----------------------------------------------------------------------------------------------------------
@@ -228,7 +254,8 @@ begin
         end process;
 
         -- mapping
-        corrout(I) <= rnd_cor;
+        corrout(I) <= rnd_cor when enable_corr='1' else
+                      avg_dout;
         corrout_fp(I) <= reg_dout2;
 
     end generate gen_corr;

hdl/corr_ll.vhd

@@ -41,6 +41,7 @@ end entity corr_ll;
 architecture rtl of corr_ll is
 
     constant C_N_A_RND  : natural := 8;
+    constant C_INT      : natural := 10;
     constant C_DELAY    : natural := 5;
     type arr_slv is array (natural range <>) of std_logic_vector;
     signal delay_valid  : std_logic_vector(C_DELAY-1 downto 0);
@@ -99,6 +100,10 @@ begin
         signal enable_corr  : std_logic;
         signal reset_corr   : std_logic;
 
+        signal integrate_dout   : signed(C_W_COR+C_INT-1 downto 0);
+        signal avg_dout         : signed(C_W_COR-1 downto 0);
+        signal integrate_cnt    : unsigned(C_INT-1 downto 0);
+
     begin
 
         -- Signal mux for X/Y coef and enable/reset, based on PSCID number
@@ -133,6 +138,9 @@ begin
                 rz_mult_a       <= (others => '0');
                 rz_mult_b       <= (others => '0');
                 rz_mult_d       <= (others => '0');
+                integrate_dout  <= (others => '0');
+                integrate_cnt   <= (others => '0');
+                avg_dout        <= (others => '0');
             elsif rising_edge(clk) then
 
                 if reset_corr = '1' then
@@ -155,10 +163,26 @@ begin
 
                 if reset_corr = '1' then
                     reg_dout    <= (others => '0');
+                    integrate_dout  <= (others => '0');
+                    integrate_cnt   <= (others => '0');
+                    avg_dout        <= (others => '0');
                 else
-                    if delay_valid(delay_valid'left-1) = '1' and enable_corr = '1' then
+                    if enable_corr = '1' then
+                        if delay_valid(delay_valid'left-1) = '1' then
                             reg_dout        <= f_resize_sat(rnd_abicd, C_W_COR);
                         end if;
+
+                        if delay_valid(3) = '1' then
+                            integrate_cnt   <= integrate_cnt-1;
+                            if integrate_cnt = 0 then
+                                avg_dout        <= integrate_dout(C_W_COR+C_INT-1 downto C_INT);
+                                integrate_dout  <= (others => '0');
+                            else
+                                integrate_dout  <= integrate_dout+reg_dout;
+                            end if;
+                        end if;
+                    end if;
+
                 end if;
 
                 -- Round and resize
@@ -184,7 +208,8 @@ begin
                            f_sum_sat(f_resize_lsb(mult_ic, rnd_abicd'length), to_signed(1, rnd_abicd'length));
 
         -- mapping
-        corrout(I) <= reg_dout;
+        corrout(I) <= reg_dout when enable_corr='1' else
+                      avg_dout;
 
     end generate gen_corr;
 

sim/generate_datasim.py

@@ -37,7 +37,7 @@ def generate_bpm_data(size, DC=0, A=0, F=100, N=0):
 #############################################################################
 N_BPM=respmat.shape[1]*2
 N_PSC=respmat.shape[0]
-size=200
+size=2000
 
 N_MM_RND=14
 
@@ -107,6 +107,9 @@ for i in range(1,size):
 
 corr = np.round(corrfp*2**-C_N_FP).astype('i2')
 
+corravg = corr[:,:1024].mean(axis=1).astype('i4')
+
+
 #############################################################################
 # Write partial and results to files
 #############################################################################
@@ -122,5 +125,8 @@ with open("corrout.txt", "w") as fp:
     for i in range(size):
         fp.write(" ".join(corr[:,i].astype("str"))+"\n")
 
+with open("corravg.txt", "w") as fp:
+    for i in range(100):
+        fp.write(" ".join(corr[i].astype("str"))+"\n")
 
 

sim/tc_basic.vhd

@@ -187,7 +187,7 @@ begin
 
         log("+-- Sending bpm packets", INFO);
         --while (not endfile(read_file)) loop
-        while nturn <  20 loop
+        while nturn <  1500 loop
             readline(read_file, line_v);
 
             for I in 0 to C_NUMBPM-1 loop