fix IIR outputs

* Proper rounding on rounded output
* Fixed point output has the same dimension as input

hdl/corr_iir.vhd

@@ -34,7 +34,7 @@ entity corr_iir is
         corrout_valid   : out std_logic;
         corrout_seq     : out std_logic_vector(C_W_BPMSEQ-1 downto 0);
         corrout         : out signed_array(0 to C_N_MM_PSC-1)(C_W_COR-1 downto 0);
-        corrout_fp      : out signed_array(0 to C_N_MM_PSC-1)(C_W_COR+C_W_FP-1 downto 0)
+        corrout_fp      : out signed_array(0 to C_N_MM_PSC-1)(C_W_MM-1 downto 0)
     );
 end entity corr_iir;
 
@@ -216,9 +216,13 @@ begin
                 ----------------------------------------------------------------------------------------------------------
                 -- Output rounding
                 if reg_dout(C_W_FP-1) = '0' then
-                    rnd_cor   <= f_resize_lsb(reg_dout, C_W_COR);
+                    rnd_cor   <= f_resize_sat(
+                                  f_resize_lsb(reg_dout, reg_dout'length-C_W_FP),
+                                 C_W_COR);
                 else
-                    rnd_cor   <= f_sum_sat(f_resize_lsb(reg_dout, C_W_COR), to_signed(1,2));
+                    rnd_cor   <= f_resize_sat(
+                                  f_sum_sat(f_resize_lsb(reg_dout, reg_dout'length-C_W_FP), to_signed(1,2)),
+                                 C_W_COR);
                 end if;
 
                 reg_dout2 <= reg_dout;
@@ -229,7 +233,7 @@ begin
 
         -- mapping
         corrout(I) <= rnd_cor;
-        corrout_fp(I) <= f_resize_sat(reg_dout2, C_W_COR+C_W_FP);
+        corrout_fp(I) <= f_resize_sat(reg_dout2, C_W_MM);
 
     end generate gen_corr;
 

hdl/top_corr_matrix.vhd

@@ -62,8 +62,7 @@ architecture struct of top_corr_matrix is
     -- Corrector result, parallel
     signal corrfirst_valid : std_logic;
     signal corrfirst_seq   : std_logic_vector(C_W_BPMSEQ-1 downto 0);
-    signal corrfirst       : signed_array(0 to C_N_MM_PSC-1)(C_W_COR+C_W_FP-1 downto 0);
-    signal corrfirst_resize: signed_array(0 to C_N_MM_PSC-1)(C_W_MM-1 downto 0);
+    signal corrfirst       : signed_array(0 to C_N_MM_PSC-1)(C_W_MM-1 downto 0);
     signal corrout_valid   : std_logic;
     signal corrout_seq     : std_logic_vector(C_W_BPMSEQ-1 downto 0);
     signal corrout         : signed_array(0 to C_N_MM_PSC-1)(C_W_COR-1 downto 0);
@@ -257,17 +256,13 @@ begin
         corrout         => open
     );
 
-    gen_resize:for I in 0 to C_N_MM_PSC-1 generate
-        corrfirst_resize(I) <= resize(corrfirst(I), C_W_MM);
-    end generate;
-
     inst_corr2: entity work.corr_iir
     port map(
         clk             => clk,
         rst_n           => rst_n,
 
         -- matmult input
-        matmult         => corrfirst_resize,
+        matmult         => corrfirst,
         matmult_valid   => corrfirst_valid,
         matmult_seq     => corrfirst_seq,