matrix_mul.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library desy;
use desy.ram_tdp;
use desy.math_signed.all;

library desyrdl;
use desyrdl.pkg_corr_matrix.t_mem_MATRIXCOEF_2d_out;
use desyrdl.pkg_corr_matrix.t_mem_MATRIXCOEF_2d_in;

use work.pkg_corr_matrix.all;

entity matrix_mul is
    port(
        clk                    : in std_logic;
        rst_n                  : in std_logic;

        -- Coef table, desyrdl
        mm_coef_i              : in t_mem_MATRIXCOEF_2d_out;
        mm_coef_o              : out t_mem_MATRIXCOEF_2d_in;
        id_cnt_load            : in std_logic_vector(C_W_MM_IDCNT-1 downto 0);

        -- Position data in
        pos_x                  : in signed(C_W_OE-1 downto 0);
        pos_y                  : in signed(C_W_OE-1 downto 0);
        pos_id                 : in std_logic_vector(C_W_BPMID-1 downto 0);
        pos_seq                : in std_logic_vector(C_W_BPMSEQ-1 downto 0);
        pos_tvalid             : in std_logic;

        -- status
        mult_rate              : out std_logic_vector(15 downto 0);
        pps                    : in std_logic;

        -- Data out
        matmult                : out signed_array(0 to C_N_MM_PSC-1)(C_W_MM-1 downto 0);
        matmult_tvalid         : out std_logic;
        matmult_seq            : out std_logic_vector(C_W_BPMSEQ-1 downto 0)

        );
end entity;

architecture rtl of matrix_mul is

    type arr_slv is array (natural range <>) of std_logic_vector;
    ------------------------
    -- SIGNAL DECLARATION --
    ------------------------
    -- delay registers
    signal r_pos_x    : signed(pos_x'left downto 0);
    signal r_pos_y    : signed(pos_y'left downto 0);
    signal r_seq      : std_logic_vector(C_W_BPMSEQ-1 downto 0);
    signal r_tvalid   : std_logic_vector(3 downto 0);


    -- Accumulators general control
    signal rst_accu     : std_logic;
    signal ena_accu     : std_logic;

    signal id_cnt       : unsigned(C_W_MM_IDCNT-1 downto 0);

    signal new_seq : std_logic;
    signal mul_done : std_logic;
    signal r_mul_done : std_logic;

    signal mul_cnt      : unsigned(15 downto 0);
    signal r_mul_cnt    : std_logic_vector(15 downto 0);
    signal pps_r        : std_logic;