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Commit 6ead1ead authored by BRONES Romain's avatar BRONES Romain
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Corrections for synthesis

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hdl/ccn_pack.vhd
+ 1
− 1
View file @ 6ead1ead
......@@ -66,7 +66,7 @@ architecture rtl of ccn_pack is
signal pkt_reg_tuser : std_logic_vector(G_S_TUSER_W-1 downto 0);
-- Sequence detector
signal prev_seq_r : std_logic_vector(8-1 downto 0);
signal prev_seq_r : std_logic_vector(G_S_TUSER_W-1 downto 0);
signal new_seq_valid_r : std_logic;
signal new_seq : std_logic;
......
hdl/ccn_unpack.vhd
+ 1
− 0
View file @ 6ead1ead
......@@ -131,6 +131,7 @@ begin
);
m_axis_tvalid <= wconv_out_tvalid;
m_axis_tlast <= wconv_out_tvalid;
m_axis_tuser <= std_logic_vector(frame_cnt(m_axis_tuser'range));
wconv_in_tvalid <= (not fsm_dump) and fifo_tvalid;
......
hdl/top_ccn_packeter.vhd
+ 34
− 27
View file @ 6ead1ead
......@@ -17,7 +17,7 @@ entity top_ccn_packeter is
G_S_TUSER_W : positive;
G_M_TUSER_W : positive;
G_M_TDATA_W : positive;
G_PROTOCOL_ID : std_logic_vector(7 downto 0)
G_PROTOCOL_ID : positive
);
port(
-- Asynchronous reset
......@@ -49,8 +49,8 @@ entity top_ccn_packeter is
s_axi_rvalid : out std_logic;
-- AXIS Packet input
s_axis_clk : in std_logic;
s_axis_tdata : in std_logic_vector(G_S_TDATA_W-1 downto 0);
s_axis_tuser : in std_logic_vector(G_S_TUSER_W-1 downto 0);
s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic;
s_axis_tlast : in std_logic;
......@@ -58,17 +58,23 @@ entity top_ccn_packeter is
-- AXIS Frame output
m_axis_clk : in std_logic; -- Only M_AXIS signals on this clk domain
m_axis_tdata : out std_logic_vector(G_M_TDATA_W-1 downto 0);
m_axis_tx_tkeep : out std_logic_vector(G_M_TDATA_W/8-1 downto 0);
m_axis_tkeep : out std_logic_vector(G_M_TDATA_W/8-1 downto 0);
m_axis_tlast : out std_logic;
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_tx_tuser : out std_logic_vector(G_M_TUSER_W-1 downto 0)
m_axis_tuser : out std_logic_vector(G_M_TUSER_W-1 downto 0)
);
end entity top_ccn_packeter;
architecture rtl of top_ccn_packeter is
-- Attributes for Xilinx Vivado Block Design
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO of m_axis_clk: SIGNAL is "xilinx.com:signal:clock:1.0 m_axis_clk CLK";
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER of m_axis_clk: SIGNAL is "ASSOCIATED_BUSIF m_axis";
------------------------
-- SIGNAL DECLARATION --
------------------------
......@@ -137,10 +143,10 @@ begin
G_S_TUSER_W => G_S_TUSER_W,
G_M_TDATA_W => G_M_TDATA_W,
G_M_TUSER_W => G_M_TUSER_W,
G_PROTOCOL_ID => G_PROTOCOL_ID
);
G_PROTOCOL_ID => std_logic_vector(to_unsigned(G_PROTOCOL_ID, 8))
)
port map(
aclk => s_axis_clk,
aclk => aclk,
aresetn => aresetn,
-- Control
......@@ -161,16 +167,17 @@ begin
s_axis_tdata => s_axis_tdata,
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tuser => s_axis_tuser,
s_axis_tlast => s_axis_tlast,
-- AXIS Frame output
m_axis_clk => m_axis_tx_clk,
m_axis_tvalid => m_axis_tx_tvalid,
m_axis_tready => m_axis_tx_tready,
m_axis_tdata => m_axis_tx_tdata,
m_axis_tkeep => m_axis_tx_tkeep,
m_axis_tlast => m_axis_tx_tlast,
m_axis_tuser => m_axis_tx_tuser
m_axis_clk => m_axis_clk,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tdata => m_axis_tdata,
m_axis_tkeep => m_axis_tkeep,
m_axis_tlast => m_axis_tlast,
m_axis_tuser => m_axis_tuser
);
......
hdl/top_ccn_unpacketer.vhd
+ 21
− 12
View file @ 6ead1ead
......@@ -16,7 +16,8 @@ entity top_ccn_unpacketer is
G_S_TDATA_W : positive;
G_S_TUSER_W : positive;
G_M_TDATA_W : positive;
G_PROTOCOL_ID : std_logic_vector(7 downto 0)
G_M_TUSER_W : positive;
G_PROTOCOL_ID : positive
);
port(
-- Asynchronous reset
......@@ -26,7 +27,7 @@ entity top_ccn_unpacketer is
timeref : in std_logic_vector(63 downto 0);
-- AXI-MM Status and Config
s_axi_clk : in std_logic;
aclk : in std_logic;
s_axi_awaddr : in std_logic_vector(C_ADDR_WIDTH-1 downto 0);
s_axi_awprot : in std_logic_vector(2 downto 0);
s_axi_awvalid : in std_logic;
......@@ -50,15 +51,15 @@ entity top_ccn_unpacketer is
-- AXIS Frame input
s_axis_clk : in std_logic; -- Only S_AXIS signals on this clk domain
s_axis_tdata : in std_logic_vector(G_S_TDATA_W-1 downto 0);
s_axis_tx_tkeep : in std_logic_vector(G_S_TDATA_W/8-1 downto 0);
s_axis_tkeep : in std_logic_vector(G_S_TDATA_W/8-1 downto 0);
s_axis_tlast : in std_logic;
s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic;
s_axis_tx_tuser : in std_logic_vector(G_S_TUSER_W-1 downto 0);
s_axis_tuser : in std_logic_vector(G_S_TUSER_W-1 downto 0);
-- AXIS Packet output
m_axis_clk : in std_logic;
m_axis_tdata : out std_logic_vector(G_M_TDATA_W-1 downto 0);
m_axis_tuser : out std_logic_vector(G_M_TUSER_W-1 downto 0);
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_tlast : out std_logic
......@@ -68,6 +69,12 @@ end entity top_ccn_unpacketer;
architecture struct of top_ccn_unpacketer is
-- Attributes for Xilinx Vivado Block Design
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO of s_axis_clk: SIGNAL is "xilinx.com:signal:clock:1.0 s_axis_clk CLK";
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER of s_axis_clk: SIGNAL is "ASSOCIATED_BUSIF s_axis";
------------------------
-- SIGNAL DECLARATION --
------------------------
......@@ -75,8 +82,8 @@ architecture struct of top_ccn_unpacketer is
signal mac_src : std_logic_vector(47 downto 0);
-- AXIMM
signal addrmap_i : t_addrmap_ccn_unpackter_in;
signal addrmap_o : t_addrmap_ccn_unpackter_out;
signal addrmap_i : t_addrmap_ccn_unpacketer_in;
signal addrmap_o : t_addrmap_ccn_unpacketer_out;
signal s_axi_m2s : t_ccn_unpacketer_m2s;
signal s_axi_s2m : t_ccn_unpacketer_s2m;
......@@ -136,10 +143,11 @@ begin
G_S_TDATA_W => G_S_TDATA_W,
G_S_TUSER_W => G_S_TUSER_W,
G_M_TDATA_W => G_M_TDATA_W,
G_PROTOCOL_ID => G_PROTOCOL_ID
);
G_M_TUSER_W => G_M_TUSER_W,
G_PROTOCOL_ID => std_logic_vector(to_unsigned(G_PROTOCOL_ID, 8))
)
port map(
rstn => rstn,
rstn => aresetn,
-- System input
pps => '0',
......@@ -164,11 +172,12 @@ begin
s_axis_tlast => s_axis_tlast,
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tx_tuser => s_axis_tx_tuser,
s_axis_tuser => s_axis_tuser,
-- AXIS Packet output
m_axis_clk => m_axis_clk,
m_axis_clk => aclk,
m_axis_tdata => m_axis_tdata,
m_axis_tuser => m_axis_tuser,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tlast => m_axis_tlast
......
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