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Commit 567bd435 authored by System User's avatar System User
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fix bug simu

parent faae391c
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sim/tb_ccn.vhd
+ 37
− 8
View file @ 567bd435
......@@ -17,7 +17,7 @@ architecture testbench of tb_ccn is
--------------------------
constant RX_COOLDOWN : natural := 0;
constant PERIOD : time := 4 ns;
constant PPS_SCALER :
constant SCALED_PPS_PERIOD : natural := 250; -- PPS = 1µs
constant PROTOCOL_ID : std_logic_vector(7 downto 0) := x"75";
constant IPKT_TDATA_W : natural := 80;
......@@ -90,15 +90,16 @@ architecture testbench of tb_ccn is
signal tx_send : boolean := false;
signal rx_recv : boolean := false;
signal tb_pps_vec : std_logic_vector(8 downto 0);
signal tb_pps_cnt : unsigned(8 downto 0);
begin
-- clock generation
tb_clk <= not tb_clk after PERIOD;
tb_m_clk <= not tb_m_clk after 6.4 ns;
-- pps generation
tb_pps <= not tb_clk after PERIOD;
--------------------------
-- DUT PACKER INSTANCIATION --
--------------------------
......@@ -113,6 +114,7 @@ begin
port map(
aclk => tb_clk,
aresetn => tb_rstn,
pps => tb_pps,
-- Control
packeter_run => tb_pack_run,
......@@ -222,18 +224,23 @@ begin
tb_unpack_mac_src <= (others => '0');
tb_unpack_mac_length <= (others => '0');
tb_unpack_enable <= '0';
tb_pkt_rate_cnt <= (others => '0');
--tb_pkt_rate_cnt <= (others => '0');
wait for 4*PERIOD;
wait until rising_edge(tb_clk);
tb_rstn <= '1';
wait until rising_edge(tb_clk);
for I in 0 to 20 loop
wait until rising_edge(tb_clk);
end loop;
-- Configuration values
tb_pack_run <= '1';
tb_unpack_enable <= '1';
......@@ -245,6 +252,7 @@ begin
tb_pack_expect_pkt <= std_logic_vector(to_unsigned(10-1, tb_pack_expect_pkt'length));
tb_pack_mac_length <= std_logic_vector(to_unsigned(10*10+10, tb_pack_mac_length'length));
tb_unpack_mac_length<= std_logic_vector(to_unsigned(10*10+10, tb_pack_mac_length'length));
--tb_pkt_rate_cnt <= (others => '0');
wait until rising_edge(tb_clk);
......@@ -255,14 +263,12 @@ begin
tx_send <= true;
rx_recv <= true;
-- Never ending end
wait;
end process p_main;
---------------
-- PPS GEN --
---------------
---------------
-- TX STREAM --
......@@ -387,5 +393,28 @@ begin
end if;
end process p_timeref;
---------------------
-- PPS GEN --
---------------------
tb_pps <= tb_pps_vec(tb_pps_vec'high) when tb_pps_vec = "100000000" else '0';
p_ppsgen: process(tb_clk, tb_rstn)
begin
if tb_rstn = '0' then
tb_pps_cnt <= (others => '0');
elsif rising_edge(tb_clk) then
if tb_pps_cnt = 256 then
tb_pps_vec <= std_logic_vector(resize(unsigned(tb_pps_cnt),tb_pps_vec'length));
tb_pps_cnt <= (others => '0');
else
tb_pps_cnt <= tb_pps_cnt+1;
tb_pps_vec <= std_logic_vector(resize(unsigned(tb_pps_cnt),tb_pps_vec'length));
end if;
end if;
end process p_ppsgen;
end architecture testbench;
sim/tb_ccn_pack.wcfg
+ 44
− 5
View file @ 567bd435
......@@ -11,15 +11,15 @@
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="0fs"></ZoomStartTime>
<ZoomEndTime time="101000001fs"></ZoomEndTime>
<Cursor1Time time="101000000fs"></Cursor1Time>
<ZoomStartTime time="2913500fs"></ZoomStartTime>
<ZoomEndTime time="9123501fs"></ZoomEndTime>
<Cursor1Time time="6316000fs"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="276"></NameColumnWidth>
<ValueColumnWidth column_width="122"></ValueColumnWidth>
<ValueColumnWidth column_width="102"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="43" />
<WVObjectSize size="52" />
<wave_markers>
<marker label="" time="5496332" />
</wave_markers>
......@@ -196,4 +196,43 @@
<obj_property name="ElementShortName">s_axis_aresetn</obj_property>
<obj_property name="ObjectShortName">s_axis_aresetn</obj_property>
</wvobject>
<wvobject fp_name="divider269" type="divider">
<obj_property name="label">OUTPUT FIFO</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_ccn/tb_pps">
<obj_property name="ElementShortName">tb_pps</obj_property>
<obj_property name="ObjectShortName">tb_pps</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_ccn/inst_dut_pack/pps">
<obj_property name="ElementShortName">pps</obj_property>
<obj_property name="ObjectShortName">pps</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_ccn/inst_dut_pack/pkt_rt_cnt">
<obj_property name="ElementShortName">pkt_rt_cnt[18:0]</obj_property>
<obj_property name="ObjectShortName">pkt_rt_cnt[18:0]</obj_property>
<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_ccn/tb_pkt_rate_cnt">
<obj_property name="ElementShortName">tb_pkt_rate_cnt[18:0]</obj_property>
<obj_property name="ObjectShortName">tb_pkt_rate_cnt[18:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_ccn/inst_dut_pack/pkt_rt_cnt_v">
<obj_property name="ElementShortName">pkt_rt_cnt_v[18:0]</obj_property>
<obj_property name="ObjectShortName">pkt_rt_cnt_v[18:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_ccn/inst_dut_pack/pkt_rt_cnt_ena">
<obj_property name="ElementShortName">pkt_rt_cnt_ena</obj_property>
<obj_property name="ObjectShortName">pkt_rt_cnt_ena</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_ccn/tb_pps_cnt">
<obj_property name="ElementShortName">tb_pps_cnt[8:0]</obj_property>
<obj_property name="ObjectShortName">tb_pps_cnt[8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_ccn/tb_pps_vec">
<obj_property name="ElementShortName">tb_pps_vec[8:0]</obj_property>
<obj_property name="ObjectShortName">tb_pps_vec[8:0]</obj_property>
</wvobject>
</wave_config>
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