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Commit 0fd7e670 authored by BRONES Romain's avatar BRONES Romain
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Merge branch 'bugfix_timeout' 

* BugFix on timeout: the fifo is properly cleared on erroneous frames.
  That fixes the bug were the packeter was stuck in timeout.
parents f7798e26 cd76e9f1
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hdl/ccn_pack.vhd
+ 27
− 13
View file @ 0fd7e670
......@@ -109,13 +109,16 @@ architecture rtl of ccn_pack is
-- Output FIFO
signal fifo_tvalid : std_logic;
signal fifo_tvalid_c : std_logic;
signal fifo_tready : std_logic;
signal fifo_tready_c : std_logic;
signal fifo_tdata : std_logic_vector(63 downto 0);
signal fifo_tkeep : std_logic_vector(7 downto 0);
signal fifo_tlast : std_logic;
signal fifo_tuser : std_logic_vector(0 downto 0);
signal fifo_tuser_slv : std_logic_vector(7 downto 0);
signal fifo_err_rst : std_logic;
signal fifo_clr : std_logic;
-- Some constant for mapping
constant C_TKEEP_S00 : std_logic_vector(23 downto 0) := (others => '1');
......@@ -235,6 +238,23 @@ begin
end if;
end process p_frame_cnt;
----------------
-- FIFO CLEAR --
----------------
p_fifo_clr:process(aclk, aresetn)
begin
if aresetn = '0' then
fifo_clr <= '0';
elsif rising_edge(aclk) then
if fifo_tuser(0) = '1' then
fifo_clr <= '1';
else
if fifo_tlast = '1' then
fifo_clr <= '0';
end if;
end if;
end if;
end process p_fifo_clr;
----------------------
-- HEADER INSERTION --
......@@ -290,7 +310,7 @@ begin
s01_axis_tlast => pkt_ix_tlast,
s01_axis_tuser => pkt_ix_tuser,
m00_axis_tvalid => fifo_tvalid,
m00_axis_tready => fifo_tready,
m00_axis_tready => fifo_tready_c,
m00_axis_tdata => fifo_tdata,
m00_axis_tkeep => fifo_tkeep,
m00_axis_tlast => fifo_tlast,
......@@ -303,14 +323,16 @@ begin
-- FIFO --
----------
fifo_tuser(0) <= or_reduce(fifo_tuser_slv);
fifo_err_rst <= (not fifo_tuser(0)) and aresetn;
fifo_err_rst <= (not fifo_clr) and aresetn;
fifo_tready_c <= fifo_tready or fifo_clr;
fifo_tvalid_c <= fifo_tvalid and not fifo_clr;
inst_fifo: entity work.ccn_axis_fifo_pframe
port map(
s_axis_aresetn => fifo_err_rst,
s_axis_aclk => aclk,
m_axis_aclk => m_axis_clk,
s_axis_tvalid => fifo_tvalid,
s_axis_tvalid => fifo_tvalid_c,
s_axis_tready => fifo_tready,
s_axis_tdata => fifo_tdata,
s_axis_tkeep => fifo_tkeep,
......@@ -386,11 +408,7 @@ begin
pass <= '0';
frame_error <= '1';
--
if pkt_ix_tready = '1' then
fsm_state_next <= STANDBY;
else
fsm_state_next <= ERR_TO;
end if;
when ERR_SEQ =>
dump <= '1';
......@@ -398,11 +416,7 @@ begin
pass <= '0';
frame_error <= '1';
--
if pkt_ix_tready = '1' then
fsm_state_next <= STANDBY;
else
fsm_state_next <= ERR_SEQ;
end if;
when others =>
dump <= '1';
......
sim/gen_testfile.py
+ 70
− 35
View file @ 0fd7e670
import numpy as np
# BPM data per sequence
bps=10
# Number of sequence
nseq=13
Nbpm=10
dty = np.dtype([("seqnum", "u2"), ("bpmid", "u2"), ("datax", "u4"), ("datay", "u4")])
# Generate a list of 16 bits words, 3 dimensions
seqdata = np.random.randint(0,2**16-1, (nseq,bps,5))
bpms=np.arange(Nbpm)+13
# Flatten last dimension, remove first sequence
seqframe = seqdata.reshape(nseq, bps*5)[1:]
def make_seq(start, nseq, bpms):
Nbpm=len(bpms)
data = np.zeros(Nbpm*nseq, dtype=dty)
data['seqnum']=np.arange(nseq, dtype="u2").repeat(Nbpm)+start
data['bpmid'] = np.tile(bpms, nseq)
data['datax']=np.random.randint(2**32-1, size=data.shape[0], dtype="u4")
data['datay']=np.random.randint(2**32-1, size=data.shape[0], dtype="u4")
return data
def make_zero(N):
data = np.zeros(N, dtype=dty)
return data
# extend to multiple of 64 bits frames
seqframe = np.hstack((seqframe, np.zeros((nseq-1, int(np.ceil(bps*5/4))*4 - bps*5), dtype=int)))
sequences = make_zero(3)
cseq= np.empty(0, dtype=dty)
s=0
blanksize=120
# Reshape to 64 bits words
seqframe = seqframe.reshape(nseq-1, seqframe.shape[1]//4, 4)
#%% 13 sequences, each followed by a blank
for n in range(13):
_s = make_seq(s,1, bpms)
sequences = np.concatenate([sequences, _s , make_zero(blanksize),])
if n!=0:
cseq = np.concatenate([cseq, _s ])
s+=1
# Generate input file
fp = open("testinput_001.txt", 'w')
for S, sdata in zip(range(nseq), seqdata):
for b, bdata in zip(range(bps), sdata):
fp.write("{:02X} ".format(S))
fp.write(("{:04X}"*5).format(*bdata[::-1]))
fp.write("\n")
fp.close()
#%% 13 sequences with missing BPM, each followed by a blank
# Generate frame file (for check)
fp = open("testframe_001.txt", 'w')
for sdata in seqframe:
for wdata in sdata:
fp.write(("{:04X}"*4).format(*wdata[::-1]))
fp.write("\n")
fp.close()
for n in range(13):
sequences = np.concatenate([sequences, make_seq(s,1, bpms[:-1]), make_zero(blanksize),])
s+=1
#%% 13 sequences, each followed by a blank
for n in range(13):
_s = make_seq(s,1, bpms)
sequences = np.concatenate([sequences, _s , make_zero(blanksize),])
if n!=0:
cseq = np.concatenate([cseq, _s ])
s+=1
#%% 13 sequences with one bpm not aligned, each followed by a blank
for n in range(13):
ws=make_seq(s,1, bpms)
ws[-4]['seqnum']=s+90
sequences = np.concatenate([sequences, ws, make_zero(blanksize),])
s+=1
#%% 13 sequences, each followed by a blank
for n in range(13):
_s = make_seq(s,1, bpms)
sequences = np.concatenate([sequences, _s , make_zero(blanksize),])
if n!=0:
cseq = np.concatenate([cseq, _s ])
s+=1
# Remove first sequence, used for startup
cseq = cseq[cseq['seqnum']!=1]
#%%
# Print to file
with open("testinput_002.txt", 'w') as fp:
for d in sequences:
fp.write("{:04X} {:04X}{:08X}{:08X}\n".format(*d))
with open("testoutput_002.txt", 'w') as fp:
for d in cseq:
fp.write("{:02X} {:04X}{:08X}{:08X}\n".format(*d))
# Generate input file
fp = open("testoutput_001.txt", 'w')
for S, sdata in zip(range(nseq-1), seqdata[2:]):
for b, bdata in zip(range(bps), sdata):
fp.write("{:02X} ".format(S+1))
fp.write(("{:04X}"*5).format(*bdata[::-1]))
fp.write("\n")
fp.close()
sim/simulate.tcl
+ 2
− 3
View file @ 0fd7e670
......@@ -5,12 +5,11 @@ set_property source_mgmt_mode All [current_project]
read_vhdl -vhdl2008 {sim/tb_ccn.vhd}
read_vhdl {hdl/ccn_unpack.vhd hdl/ccn_pack.vhd}
read_vhdl {hdl/pkg_bpmpacket_stream.vhd}
add_files -fileset sim_1 {sim/testinput_001.txt sim/testframe_001.txt sim/testoutput_001.txt }
add_files -fileset sim_1 {sim/testinput.txt sim/testoutput.txt }
set CCN_DPKT_W 80
set CCN_UPKT_W 80
set CCN_DPKT_TU_W 8
set CCN_DPKT_TU_W 16
set CCN_UPKT_TU_W 8
set CCN_FRAME_W 64
set CCN_FRAME_HEADER_W 192
......
sim/tb_ccn.vhd
+ 14
− 70
View file @ 0fd7e670
......@@ -20,7 +20,7 @@ architecture testbench of tb_ccn is
constant PROTOCOL_ID : std_logic_vector(7 downto 0) := x"75";
constant IPKT_TDATA_W : natural := 80;
constant IPKT_TUSER_W : natural := 8;
constant IPKT_TUSER_W : natural := 16;
constant OPKT_TDATA_W : natural := 80;
constant OPKT_TUSER_W : natural := 8;
constant FRAME_TDATA_W : natural := 64;
......@@ -37,7 +37,6 @@ architecture testbench of tb_ccn is
-- Input packet axis
signal tb_s_axis_tuser : std_logic_vector(IPKT_TUSER_W-1 downto 0);
signal tb_s_axis_tdata : std_logic_vector(IPKT_TDATA_W-1 downto 0);
signal tb_s_axis_tlast : std_logic;
signal tb_s_axis_tvalid : std_logic;
signal tb_s_axis_tready : std_logic;
......@@ -115,13 +114,13 @@ begin
packet_timeout => tb_pack_timeout,
expect_pkt_cnt => tb_pack_expect_pkt,
timeref => std_logic_vector(tb_timeref),
latch_seq => '0',
-- AXIS Packet input
s_axis_tdata => tb_s_axis_tdata,
s_axis_tuser => tb_s_axis_tuser,
s_axis_tvalid => tb_s_axis_tvalid,
s_axis_tready => tb_s_axis_tready,
s_axis_tlast => tb_s_axis_tlast,
-- AXIS Frame output
m_axis_clk => tb_m_clk,
......@@ -132,6 +131,8 @@ begin
m_axis_tlast => eth_axis_tlast,
m_axis_tuser => eth_axis_tuser,
latched_seq1 => open,
latched_seq2 => open,
status_err_seq => tb_pack_err_seq,
status_err_timeout => tb_pack_err_timeout,
status_frame_count => tb_pack_frame_count
......@@ -165,6 +166,7 @@ begin
err_mac_dst => tb_unpack_err_mac_dst,
err_mac_src => tb_unpack_err_mac_src,
pkt_mcts => tb_unpack_mcts,
frame_counter => open,
-- AXIS Frame input
s_axis_clk => tb_m_clk,
......@@ -224,14 +226,14 @@ begin
-- Configuration values
tb_pack_run <= '1';
tb_unpack_enable <= '1';
tb_pack_timeout <= x"0600";
tb_pack_timeout <= x"0040";
tb_pack_mac_dst <= x"010000DBAAFF";
tb_pack_mac_src <= x"050000DBAAFF";
tb_unpack_mac_dst <= x"010000DBAAFF";
tb_unpack_mac_src <= x"050000DBAAFF";
tb_pack_expect_pkt <= std_logic_vector(to_unsigned(10-1, tb_pack_expect_pkt'length));
tb_pack_mac_length <= std_logic_vector(to_unsigned(10*10+9, tb_pack_mac_length'length));
tb_unpack_mac_length<= std_logic_vector(to_unsigned(10*10+9, tb_pack_mac_length'length));
tb_pack_mac_length <= std_logic_vector(to_unsigned(10*10+10, tb_pack_mac_length'length));
tb_unpack_mac_length<= std_logic_vector(to_unsigned(10*10+10, tb_pack_mac_length'length));
wait until rising_edge(tb_clk);
-- Enable RX after a time
......@@ -252,7 +254,7 @@ begin
---------------
p_tx_send:process
file testinput : TEXT open READ_MODE is "testinput_001.txt";
file testinput : TEXT open READ_MODE is "testinput.txt";
variable linenum : natural :=0;
variable text_line : line;
variable readok : boolean;
......@@ -285,10 +287,11 @@ begin
assert readok
report "Read 'tdata' failed for line: " & integer'image(linenum) severity failure;
tb_s_axis_tdata <= vr_tdata;
tb_s_axis_tuser <= vr_tuser;
tb_s_axis_tvalid <= '1';
tb_s_axis_tlast <= '1';
-- Special on data=0, just let it roll as if no data ready
tb_s_axis_tvalid <= '1' when unsigned(vr_tdata) /= 0 else '0';
wait until rising_edge(tb_clk) and tb_s_axis_tready='1';
tb_s_axis_tvalid <= '0';
......@@ -304,7 +307,7 @@ begin
---------------
p_rx_recv:process
file testoutput : TEXT open READ_MODE is "testoutput_001.txt";
file testoutput : TEXT open READ_MODE is "testoutput.txt";
variable linenum : natural :=0;
variable text_line : line;
variable readok : boolean;
......@@ -357,65 +360,6 @@ begin
end loop;
end process p_rx_recv;
------------------
-- FRAME STREAM --
------------------
p_frame_stream:process
file testframe : TEXT open READ_MODE is "testframe_001.txt";
variable linenum : natural :=0;
variable text_line : line;
variable readok : boolean;
variable vr_tdata : std_logic_vector(FRAME_TDATA_W-1 downto 0);
variable masked_tdata : std_logic_vector(FRAME_TDATA_W-1 downto 0);
variable vr_cnt : natural := 0;
begin
while true loop
wait until
(rising_edge(tb_m_clk) and
eth_axis_tvalid = '1' and
eth_axis_tready = '1');
for I in 0 to FRAME_TDATA_W/8-1 loop
if eth_axis_tkeep(I) = '1' then
masked_tdata((I+1)*8-1 downto I*8) := eth_axis_tdata((I+1)*8-1 downto I*8);
else
masked_tdata((I+1)*8-1 downto I*8) := (others => '0');
end if;
end loop;
if vr_cnt > 2 then
if endfile(testframe) then
report "End of file reached." severity warning;
exit;
end if;
readline(testframe, text_line);
linenum := linenum+1;
hread(text_line, vr_tdata, readok);
assert readok
report "Read 'tdata' failed for line: " & integer'image(linenum) severity failure;
assert masked_tdata = vr_tdata
report "Frame check mismatch. Got " & to_hex_string(masked_tdata) & " ; Expected " & to_hex_string(vr_tdata)
severity warning;
if eth_axis_tlast = '1' then
vr_cnt := 0;
end if;
else
vr_cnt := vr_cnt+1;
end if;
end loop;
end process;
---------------------
-- TIMEREF COUNTER --
---------------------
......
sim/tb_ccn_pack.wcfg
+ 15
− 7
View file @ 0fd7e670
......@@ -11,15 +11,18 @@
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="355363fs"></ZoomStartTime>
<ZoomEndTime time="1310364fs"></ZoomEndTime>
<Cursor1Time time="1440000fs"></Cursor1Time>
<ZoomStartTime time="0fs"></ZoomStartTime>
<ZoomEndTime time="101000001fs"></ZoomEndTime>
<Cursor1Time time="101000000fs"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="276"></NameColumnWidth>
<ValueColumnWidth column_width="265"></ValueColumnWidth>
<ValueColumnWidth column_width="122"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="42" />
<WVObjectSize size="43" />
<wave_markers>
<marker label="" time="5496332" />
</wave_markers>
<wvobject fp_name="divider58" type="divider">
<obj_property name="label">AXIS input</obj_property>
<obj_property name="DisplayName">label</obj_property>
......@@ -29,8 +32,9 @@
<obj_property name="ObjectShortName">s_axis_tdata[79:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_ccn/inst_dut_pack/s_axis_tuser">
<obj_property name="ElementShortName">s_axis_tuser[7:0]</obj_property>
<obj_property name="ObjectShortName">s_axis_tuser[7:0]</obj_property>
<obj_property name="ElementShortName">s_axis_tuser[15:0]</obj_property>
<obj_property name="ObjectShortName">s_axis_tuser[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_ccn/inst_dut_pack/s_axis_tvalid">
<obj_property name="ElementShortName">s_axis_tvalid</obj_property>
......@@ -188,4 +192,8 @@
<obj_property name="ElementShortName">m_axis_tuser[0:0]</obj_property>
<obj_property name="ObjectShortName">m_axis_tuser[0:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_ccn/inst_dut_pack/inst_fifo/s_axis_aresetn">
<obj_property name="ElementShortName">s_axis_aresetn</obj_property>
<obj_property name="ObjectShortName">s_axis_aresetn</obj_property>
</wvobject>
</wave_config>
sim/tb_test.vhd deleted 100644 → 0
+ 0
− 76
View file @ f7798e26
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity tb_test is
end entity;
architecture testbench of tb_test is
signal tb_clk : std_logic := '0';
signal posx : std_logic_vector(31 downto 0);
signal sendfile: boolean := false;
file testinput : TEXT;
--file testinput : TEXT open READ_MODE is "testinput_001.txt";
begin
tb_clk <= not tb_clk after 5 ns;
main_proc:process
begin
wait for 50 ns;
file_open(testinput, "testinput_001.txt", read_mode);
sendfile <= true;
wait for 50 ns;
wait;
end process;
read_proc:process
variable linenum : positive :=0;
variable text_line : line;
variable text_line_cc : line;
variable readok : boolean;
variable vr_posx : std_logic_vector(31 downto 0);
begin
while true loop
wait until sendfile;
while not endfile(testinput) loop
wait until rising_edge(tb_clk);
readline(testinput, text_line);
linenum := linenum+1;
report "Read: "&text_line.all severity note;
-- Skip empty lines and single-line comments
if text_line.all'length = 0 or text_line.all(1) = '#' then
next;
end if;
hread(text_line, vr_posx, readok);
assert readok
report "Read 'posx' failed for line: " & integer'image(linenum) severity failure;
posx <= vr_posx;
end loop;
sendfile <= false;
file_close(testinput);
end loop;
end process read_proc;
end architecture;
sim/testinput.txt 0 → 120000
+ 1
− 0
View file @ 0fd7e670
testinput_002.txt
\ No newline at end of file
sim/testoutput.txt 0 → 120000
+ 1
− 0
View file @ 0fd7e670
testoutput_002.txt
\ No newline at end of file
tcl/generate_axis.tcl
+ 1
− 1
View file @ 0fd7e670
......@@ -47,7 +47,7 @@ set_property -dict [list \
CONFIG.C_NUM_SI_SLOTS {2} \
CONFIG.C_NUM_MI_SLOTS {1} \
CONFIG.C_M00_AXIS_IS_ACLK_ASYNC 0 \
CONFIG.C_M00_AXIS_REG_CONFIG 0 \
CONFIG.C_M00_AXIS_REG_CONFIG 1 \
CONFIG.C_S00_AXIS_IS_ACLK_ASYNC 0 \
CONFIG.C_S00_AXIS_REG_CONFIG 0 \
CONFIG.C_S01_AXIS_IS_ACLK_ASYNC 0 \
......
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