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comcellnode_ethernet

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COMCELLNODE ETHERNET module documentation


Description


This module instantiate the Xilinx Ethernet Subsystem for 10 GbE communication.


The GT wizard core is separated from the Ethernet Subsystem, to allow different transceivers form one quad to run different communication type (ie Gbe and COMBPM).


Overview


Main operation: Top level

This module is mainly structural, connecting the IP blocks with the control and status of the AXI-MM interface.


The QPLL core shall be instanciated by the application, providing a 156.25 MHz clock ref.


Figure 1. Basic overview of comcell ethernet module


Registers map


Table 1. Register


Name
N
bits
type
RW
Description


VERSION
1
32
uint
RO
Module version.


GT_CONTROL
1
9
uint
RW
GT core control.  

- RST_TX_CLK [0:0] sw:RW uint : Reset transmitter clock. 

- RST_RX_CLK [1:1] sw:RW uint : Reset receiver clock. 

- RST_TX_DATA [2:2] sw:RW uint : Reset transmitter datapath. 

- RST_RX_DATA [3:3] sw:RW uint : Reset receiver datapath. 

- RST_TX [4:4] sw:RW uint : Global reset on transmitter. 

- RST_RX [5:5] sw:RW uint : Global reset on receiver. 

- LOOPBACK [8:6] sw:RW uint : Loopback on the GT. See Xilinx doc.


GT_STATUS
1
7
uint
RO
GT core status.  

- CDR_STABLE [0:0] sw:RO uint : Clock Data Recovery is stable. 

- SFP_RX_LOS [1:1] sw:RO uint : Receiver loss indicator on the SFP module. 

- SFP_MOD_ABS [2:2] sw:RO uint : SFP module is absent. 

- SFP_TX_FAULT [3:3] sw:RO uint : Transmitter fault on the SFP module. 

- TX_CLK_ACTIVE [4:4] sw:RO uint : Transmitter clock is active. 

- RX_CLK_ACTIVE [5:5] sw:RO uint : Receiver clock is active. 

- POWERGOOD [6:6] sw:RO uint : Powergood on GT core.


Table 2. External address maps


Name
size
address
interface
Description


ETH
2336
0x00001000
AXI4L
Xilinx Ethernet Subsystem registers.


TODO/Future of this module