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Created with Raphaël 2.2.010Oct21Feb230Oct2430May4Apr17Feb13107Nov14Oct67Sep30Aug251621Jun1615141320May19185Add CDC between AXIMM and logicdevdevfix: Corrections on reset engine1.1 fix1.1 fixchore: add licensefix: Change reset engineRemove PPS edge filter1.0 master1.0 masterfix: Set pm_tick on all CCN corefeat:Add pps input for ethernet statisticsfix(rdl): specify hw accessfeat:Bring GT powergood signal to top level interfacefeat:Rename to CCN, Configuration of GTH_LOCwip: add generate+generic based instanciationWip:Rename to CCN, add 4 component declarationWIP:use integer index, independant of LOCWip: same top level but use configurationsChanging IP generation scriptRemoving useless filesMoving component declaration in packageTCL: Remove FPGA part setSmall correction after RDL change.Add documentation, update RDLFix polarity on DESYRDLCorrection for ImplementationRemove packeter from this moduleChange addressmap capitalizationCosmetics on namingRename for addrmapConnect AXI-MM in top levelCorrection on addressmap and RDLCorrection on RDLAdd FWK TCL and RDL filesWIP New top levelAdd header insertionWIP Add timeout featureWIP corrections for simulationWIP Add BPM packeterDebug and fixesAdd Reset Helper to handle the reset sequenceInvert GT ResetDone before feeding eth subsystemFix Address Range on AXI-MMAdd debug output

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