Skip to content
Snippets Groups Projects

Compare revisions

Changes are shown as if the source revision was being merged into the target revision. Learn more about comparing revisions.

Source

Select target project
No results found
Select Git revision
Loading items

Target

Select target project
  • dg/fofb/com_bpm
1 result
Select Git revision
Loading items
Show changes
################################################################################
# Main tcl for the module
################################################################################
# ==============================================================================
proc init {} {
# Configuration
# TODO Follow FWK
# variable quad_name
# set quad_name X0Y4
}
# ==============================================================================
proc setSources {} {
variable Vhdl
# Generate VHDL package with modversion
genModVerFile VHDL ../hdl/pkg_combpm_version.vhd
lappend Vhdl ../hdl/pkg_combpm_version.vhd
lappend Vhdl ../hdl/combpm_protocol_electron.vhd
lappend Vhdl ../hdl/top_combpm_electron.vhd
lappend Vhdl ../hdl/pkg_bpmpacket_stream.vhd
lappend Vhdl ../hdl/combpm_packet_filter.vhd
}
# ==============================================================================
proc setAddressSpace {} {
variable AddressSpace
addAddressSpace AddressSpace "combpm" RDL {} ../rdl/combpm.rdl
}
# ==============================================================================
proc doOnCreate {} {
# This module is only for vivado tool. End here for another tooltype.
if {$::fwfwk::ToolType ne "vivado"} {
puts "\n[ERROR] This module is only configured to work with Vivado"
exit -1
}
# Create GT wizard IP
set_property part ${::fwfwk::FpgaPart} [current_project]
set_property target_language VHDL [current_project]
source combpm_gtwizard.tcl
source generate_combpm_packet_filter_ip.tcl
variable Vhdl
addSources Vhdl
}
# ==============================================================================
proc doOnBuild {} {
}
# ==============================================================================
proc setSim {} {
}