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doc/images/overview.svg
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doc/main.adoc
View file @ 73ef0ccf
= COMBPM module documentation
|===
| MODULE ID | 0x507E1710 | (1350440720)
|===
// ================================================================================
== Description
This module provides several logic blocks to allow communication with BPM (Beam Position Monitor) electronics.
......@@ -8,21 +12,25 @@ This has been built for a very precise situation (libera electron, damc-fmc2zup)
For now, it only provides RX communication from the DLS CC protocol (ITech libera electron).
The module has been designed for DAMC-FMC2ZUP targets, populated with a 4SFP+ FMC board (CAENels).
**Requires DESY VHDL LIB (dual port ram)**
// ================================================================================
== Overview
=== Main operation: Top level
The basics of this module is in three blocs that are essentials for the application.
The basics of this module is in four blocs that are essentials for the application.
* *Transceiver bloc*. Used to deserialize the communication stream from the BPM. +
_For now it is a Xilinx GTWizard, configured for the Libera Electron DLS CC protocol specs (2Gbps, 16b words...)._
_This is tied to a specific transceiver input of the FPGA._
_This is tied to a specific transceiver input (X0Y4) of the FPGA._
* *Protocol decoder bloc*. From the deserialized words, it decode the stream and get the essential data (BPM number, position, timestamp...).
It outputs it on a AXI-Stream interface. +
_For now, it parses Libera Electron DLS CC._
* *Packet filter*. Filter packets based on the BPMID and can translate a value to the TDEST field of the AXIS output.
* *AXI-MM register interface*. Used to configure and monitor everything from an AXI-MM interface (CPU).
These three blocs are depicted in the image below.
......@@ -33,12 +41,6 @@ _The actual __top_combpm_electron.vhd__ file provides these three blocs configur
.Basic overview of combpm module
image::images/overview.svg[]
=== Additionnal blocs
The module provide additionnal blocs usefull for the application.
* Packet filter
=== Package
A package describing the AXIS packet at the module output is present.
......@@ -107,7 +109,7 @@ We use DESYRDL to generate a AXI4L slave decoder.
This block can drop BPM packets from the AXIS by looking up their BPM_ID field.
A simple memory block is used and programmed via the AXI-MM interface.
The block is adressed by the BPM ID (0 to 255).
The block is addressed by the BPM ID (0 to 255).
The msb (bit 7) gives the forward signal.
If '1' then the packet is transfered, else it is blocked.
......@@ -115,8 +117,6 @@ If '1' then the packet is transfered, else it is blocked.
The 6 lsb (bit 6-0) is filled into the TDEST field of the AXIS stream.
This can be used to further routing.
.Structural schematic of combpm_packet_filter.
image::images/combpm_packet_filter.svg[]
// ================================================================================
== Registers map
......@@ -125,6 +125,7 @@ include::regmap.adoc[]
// ================================================================================
== TODO/Future of this module
* Remove the pkg bpm stream. It is not that handy.
* Add configuration feature to allow the choice of the transceiver (for now only X0Y4 GTH).
* The application should be able to instanciate several transceiver interface, with one decoder for each.
* At SOLEIL, the BPM electronics will change by 2025.
......
doc/regmap.adoc
View file @ 73ef0ccf
......@@ -30,6 +30,7 @@
| VALIDFRAMERATE | 1 | 32 | uint | RO | +++BPM protocol valid frame rate+++
| INVALIDFRAMERATE | 1 | 32 | uint | RO | +++BPM protocol invalid frame rate+++
| FRAMESEQ | 1 | 16 | uint | RO | +++BPM protocol frame sequence+++
| TABLE | 256 | 8 | uint | RW | +++Packet filter table+++
|===
hdl/combpm_packet_filter.vhd
View file @ 73ef0ccf
......@@ -4,145 +4,47 @@ use ieee.numeric_std.all;
use work.pkg_bpmpacket_stream.all;
library desy;
use desy.ram_tdp;
entity combpm_packet_filter is
generic(
G_B_ADDR_W : natural := 14
G_W_ADDR_TABLE : natural
);
port(
axis_clk : in std_logic;
axi_clk : in std_logic;
axis_rst_n : in std_logic;
axi_rst_n : in std_logic;
-- AXIS SLAVE INTERFACE
s_axis_tdest : in std_logic_vector(C_TDEST_W-1 downto 0);
s_axis_tdata : in std_logic_vector(C_TDATA_W-1 downto 0);
s_axis_tlast : in std_logic;
s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic;
axis_clk : in std_logic;
axi_clk : in std_logic;
axis_rst_n : in std_logic;
-- AXIS SLAVE INTERFACE
m_axis_tdest : out std_logic_vector(C_TDEST_W-1 downto 0);
m_axis_tdata : out std_logic_vector(C_TDATA_W-1 downto 0);
m_axis_tlast : out std_logic;
m_axis_tvalid : out std_logic;
s_axis_tdest : in std_logic_vector(C_TDEST_W-1 downto 0);
s_axis_tdata : in std_logic_vector(C_TDATA_W-1 downto 0);
s_axis_tvalid : in std_logic;
-- AXIS MASTER INTERFACE
m_axis_tdest : out std_logic_vector(C_TDEST_W-1 downto 0);
m_axis_tdata : out std_logic_vector(C_TDATA_W-1 downto 0);
m_axis_tvalid : out std_logic;
-- Table configuration interface
pi_table_en : in std_logic;
pi_table_we : in std_logic;
pi_table_addr : in std_logic_vector(G_W_ADDR_TABLE-1 downto 0);
pi_table_data : in std_logic_vector(7 downto 0);
po_table_data : out std_logic_vector(7 downto 0)
-- AXI bus interface
s_axi_awaddr : IN STD_LOGIC_VECTOR(G_B_ADDR_W-1 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(G_B_ADDR_W-1 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
end combpm_packet_filter;
architecture rtl of combpm_packet_filter is
---------------------------
-- COMPONENT DECLARATION --
---------------------------
COMPONENT combpm_packet_filter_axi_bram_ctrl
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(G_B_ADDR_W-1 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(G_B_ADDR_W-1 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(G_B_ADDR_W-1 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT combpm_packet_filter_blk_mem
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(G_B_ADDR_W-3 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(G_B_ADDR_W-1 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
-- SIGNAL DECLARATION --
------------------------
signal in_packet : t_bpmpacket;
signal out_packet : t_bpmpacket;
signal bram_clk_a : STD_LOGIC;
signal bram_en_a : STD_LOGIC;
signal bram_we_a : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal bram_addr_a : STD_LOGIC_VECTOR(G_B_ADDR_W-3 DOWNTO 0);
signal bram_wrdata_a : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal bram_rddata_a : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal table_data : std_logic_vector(7 downto 0);
signal tvalid_r : std_logic_vector(1 downto 0);
......@@ -152,9 +54,6 @@ begin
zero_packet <= (others => '0');
-- always ready
s_axis_tready <= '1';
----------------------
-- STREAM REGISTERS --
----------------------
......@@ -183,76 +82,30 @@ begin
-----------------
m_axis_tdest <= std_logic_vector(resize(unsigned(table_data(6 downto 0)), C_TDEST_W));
m_axis_tdata <= bpmpacket2slv(out_packet);
m_axis_tlast <= '1'; -- Packet is one tdata only
m_axis_tvalid <= tvalid_r(tvalid_r'left) and table_data(7);
---------------------
-- BRAM CONTROLLER --
---------------------
inst_bram_ctrl : combpm_packet_filter_axi_bram_ctrl
port map (
s_axi_aclk => axi_clk,
s_axi_aresetn => axi_rst_n,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
bram_rst_a => open,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a(1 downto 0) => open,
bram_addr_a(G_B_ADDR_W-1 downto 2) => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a
);
-------------------
-- BRAM INSTANCE --
-------------------
inst_bram : combpm_packet_filter_blk_mem
------------------
-- FILTER TABLE --
------------------
-- Port A is read write from AXI controller, Port B is read only from logic
inst_phase_table: entity desy.ram_tdp
generic map(
G_ADDR => G_W_ADDR_TABLE,
G_DATA => 8
)
port map(
clka => bram_clk_a,
ena => bram_en_a,
wea => bram_we_a,
addra => bram_addr_a,
dina => bram_wrdata_a,
douta => bram_rddata_a,
clkb => axis_clk,
enb => '1',
web => "0",
addrb => in_packet.bpm_id(G_B_ADDR_W-1 downto 0),
dinb => (others => '0'),
doutb => table_data
pi_clk_a => axi_clk,
pi_en_a => pi_table_en,
pi_we_a => pi_table_we,
pi_addr_a => pi_table_addr,
pi_data_a => pi_table_data,
po_data_a => po_table_data,
pi_clk_b => axis_clk,
pi_en_b => '1',
pi_we_b => '0',
pi_addr_b => in_packet.bpm_id(G_W_ADDR_TABLE-1 downto 0),
pi_data_b => (others => '0'),
po_data_b => table_data
);
end architecture rtl;
hdl/pkg_combpm.vhd 0 → 100644
View file @ 73ef0ccf
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pkg_combpm is
constant C_W_ADDR_TABLE : natural := 8;
-------------------------
-- GT WIZARD COMPONENT --
-------------------------
COMPONENT combpm_gtwizard
PORT (
gtwiz_userclk_tx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_srcclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_usrclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_usrclk2_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_active_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_srcclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_usrclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_usrclk2_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_active_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_clk_freerun_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_all_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_tx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_tx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_qpll1lock_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_cdr_stable_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_tx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_qpll1reset_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userdata_tx_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
gtwiz_userdata_rx_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
gthrxn_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gthrxp_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
qpll0clk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
qpll0refclk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
qpll1clk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
qpll1refclk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
rx8b10ben_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
rxbufreset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
rxcommadeten_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
rxmcommaalignen_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
rxpcommaalignen_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
tx8b10ben_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
txctrl0_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
txctrl1_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
txctrl2_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gthtxn_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gthtxp_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtpowergood_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
rxbufstatus_out : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
rxbyteisaligned_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
rxbyterealign_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
rxcdrlock_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
rxclkcorcnt_out : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
rxcommadet_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
rxctrl0_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rxctrl1_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rxctrl2_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
rxctrl3_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
rxpmaresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
txpmaresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
end package;
\ No newline at end of file
hdl/top_combpm_electron.vhd
View file @ 73ef0ccf
......@@ -15,6 +15,7 @@ use desyrdl.pkg_combpm.all;
use work.pkg_bpmpacket_stream.all;
use work.pkg_combpm_version.all;
use work.pkg_combpm.all;
entity top_combpm_electron is
port(
......@@ -22,7 +23,6 @@ entity top_combpm_electron is
rst_n : in std_logic; -- Asynchronous reset
free_100_clk : in std_logic; -- Freerunning clock for GT
pps : in std_logic; -- A pulse per second signal, sync to clk domain
clk : out std_logic; -- main clock (AXIS and AXI-MM)
mc_time : in std_logic_vector(39 downto 0);
-- Transceiver QPLL interface
......@@ -47,75 +47,20 @@ entity top_combpm_electron is
sfp_tx_fault : in std_logic;
-- AXIS interface
m_axis_m2s : out t_bpmpacket_axis_m2s;
m_axis_s2m : in t_bpmpacket_axis_s2m; -- warning: TREADY is ignored !
m_axis_aclk : out std_logic;
m_axis_tdata : out std_logic_vector(C_TDATA_W-1 downto 0);
m_axis_tdest : out std_logic_vector(C_TDEST_W-1 downto 0);
m_axis_tvalid : out std_logic;
-- AXI bus interface
pi_s_top : in t_COMBPM_m2s;
po_s_top : out t_COMBPM_s2m
s_axi_aclk : in std_logic;
s_axi_m2s : in t_combpm_m2s;
s_axi_s2m : out t_combpm_s2m
);
end top_combpm_electron;
architecture struct of top_combpm_electron is
COMPONENT combpm_gtwizard
PORT (
gtwiz_userclk_tx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_srcclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_usrclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_usrclk2_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_active_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_srcclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_usrclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_usrclk2_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_active_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_clk_freerun_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_all_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_tx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_tx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_qpll1lock_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_cdr_stable_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_tx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_qpll1reset_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userdata_tx_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
gtwiz_userdata_rx_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
gthrxn_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gthrxp_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
qpll0clk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
qpll0refclk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
qpll1clk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
qpll1refclk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
rx8b10ben_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
rxbufreset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
rxcommadeten_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
rxmcommaalignen_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
rxpcommaalignen_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
tx8b10ben_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
txctrl0_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
txctrl1_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
txctrl2_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gthtxn_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gthtxp_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtpowergood_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
rxbufstatus_out : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
rxbyteisaligned_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
rxbyterealign_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
rxcdrlock_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
rxclkcorcnt_out : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
rxcommadet_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
rxctrl0_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rxctrl1_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rxctrl2_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
rxctrl3_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
rxpmaresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
txpmaresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
------------------------
-- SIGNAL DECLARATION --
------------------------
......@@ -144,6 +89,14 @@ architecture struct of top_combpm_electron is
signal addrmap_w : t_addrmap_combpm_in;
signal addrmap_r : t_addrmap_combpm_out;
signal cdc_status_array_axi : std_logic_vector(155 downto 0); -- CDC, clock axi side
signal cdc_status_array_bpm : std_logic_vector(155 downto 0); -- CDC, clock bpm side
signal cdc_control_array_axi : std_logic_vector(2 downto 0); -- CDC, clock axi side
signal cdc_control_array_bpm : std_logic_vector(2 downto 0); -- CDC, clock bpm side
signal m_axis_decoded_m2s : t_bpmpacket_axis_m2s;
signal m_axis_decoded_s2m : t_bpmpacket_axis_s2m; -- warning: TREADY is ignored !
begin
......@@ -177,7 +130,7 @@ begin
error_detect <= frame_error or cnt_seq_mismatch or seq_discontinuity;
-- Output clock
clk <= usrclk;
m_axis_aclk <= usrclk;
-- SFP direct connexion
sfp_tx_disable <= '1';
......@@ -189,38 +142,87 @@ begin
begin
inst_aximm: entity desyrdl.combpm
port map(
pi_clock => usrclk,
pi_clock => s_axi_aclk,
pi_reset => sync_reset,
pi_s_top => pi_s_top,
po_s_top => po_s_top,
pi_s_top => s_axi_m2s,
po_s_top => s_axi_s2m,
pi_addrmap => addrmap_w,
po_addrmap => addrmap_r
);
addrmap_w.ID.data.data <= x"507E1710";
addrmap_w.VERSION.data.data <= C_VERSION;
addrmap_w.SFP.RXLOS.data(0) <= sfp_rx_los;
addrmap_w.SFP.MODABS.data(0) <= sfp_mod_abs;
addrmap_w.GT.POWERGOOD.data(0) <= gt_powergood;
addrmap_w.GT.QPLLLOCK.data(0) <= qpll_lock;
addrmap_w.GT.RXCDRLOCK.data(0) <= gt_rxcdrlock;
addrmap_w.GT.RXRESETDONE.data(0) <= gt_rxresetdone;
addrmap_w.GT.RXBYTEISALIGNED.data(0) <= gt_rxbyteisaligned;
addrmap_w.GT.RXBYTEREALIGN.data(0) <= gt_rxbyterealign;
addrmap_w.GT.RXCOMMADET.data(0) <= gt_rxcommadet;
cdc_status_array_bpm(0) <= sfp_rx_los;
cdc_status_array_bpm(1) <= sfp_mod_abs;
cdc_status_array_bpm(2) <= gt_powergood;
cdc_status_array_bpm(3) <= qpll_lock;
cdc_status_array_bpm(4) <= gt_rxcdrlock;
cdc_status_array_bpm(5) <= gt_rxresetdone;
cdc_status_array_bpm(6) <= gt_rxbyteisaligned;
cdc_status_array_bpm(7) <= gt_rxbyterealign;
cdc_status_array_bpm(8) <= gt_rxcommadet;
cdc_status_array_bpm(9) <= frame_error;
cdc_status_array_bpm(10) <= cnt_seq_mismatch;
cdc_status_array_bpm(11) <= seq_discontinuity;
cdc_status_array_bpm(43 downto 12) <= frame_valid_cnt;
cdc_status_array_bpm(75 downto 44) <= frame_invalid_cnt;
cdc_status_array_bpm(107 downto 76) <= frame_valid_rate;
cdc_status_array_bpm(139 downto 108) <= frame_invalid_rate;
cdc_status_array_bpm(155 downto 140) <= frame_seq_cnt;
inst_xpm_cdc_status_array_single: xpm_cdc_array_single
generic map (
DEST_SYNC_FF => 4,
INIT_SYNC_FF => 0,
SIM_ASSERT_CHK => 0,
SRC_INPUT_REG => 1,
WIDTH => cdc_status_array_axi'length
)
port map (
dest_out => cdc_status_array_axi,
dest_clk => s_axi_aclk,
src_clk => usrclk,
src_in => cdc_status_array_bpm
);
addrmap_w.PROTOCOL.FRAMEERROR.data(0) <= frame_error;
addrmap_w.PROTOCOL.SEQFRAMECNTERROR.data(0) <= cnt_seq_mismatch;
addrmap_w.PROTOCOL.SEQFRAMEDISCONT.data(0) <= seq_discontinuity;
inst_xpm_cdc_control_array_single: xpm_cdc_array_single
generic map (
DEST_SYNC_FF => 4,
INIT_SYNC_FF => 0,
SIM_ASSERT_CHK => 0,
SRC_INPUT_REG => 1,
WIDTH => cdc_control_array_axi'length
)
port map (
dest_out => cdc_control_array_bpm,
dest_clk => usrclk,
src_clk => s_axi_aclk,
src_in => cdc_control_array_axi
);
addrmap_w.VALIDFRAMECNT.data.data <= frame_valid_cnt;
addrmap_w.INVALIDFRAMECNT.data.data <= frame_invalid_cnt;
addrmap_w.VALIDFRAMERATE.data.data <= frame_valid_rate;
addrmap_w.INVALIDFRAMERATE.data.data <= frame_invalid_rate;
addrmap_w.FRAMESEQ.data.data <= frame_seq_cnt;
addrmap_w.SFP.RXLOS.data(0) <= cdc_status_array_axi(0);
addrmap_w.SFP.MODABS.data(0) <= cdc_status_array_axi(1);
addrmap_w.GT.POWERGOOD.data(0) <= cdc_status_array_axi(2);
addrmap_w.GT.QPLLLOCK.data(0) <= cdc_status_array_axi(3);
addrmap_w.GT.RXCDRLOCK.data(0) <= cdc_status_array_axi(4);
addrmap_w.GT.RXRESETDONE.data(0) <= cdc_status_array_axi(5);
addrmap_w.GT.RXBYTEISALIGNED.data(0) <= cdc_status_array_axi(6);
addrmap_w.GT.RXBYTEREALIGN.data(0) <= cdc_status_array_axi(7);
addrmap_w.GT.RXCOMMADET.data(0) <= cdc_status_array_axi(8);
addrmap_w.PROTOCOL.FRAMEERROR.data(0) <= cdc_status_array_axi(9);
addrmap_w.PROTOCOL.SEQFRAMECNTERROR.data(0) <= cdc_status_array_axi(10);
addrmap_w.PROTOCOL.SEQFRAMEDISCONT.data(0) <= cdc_status_array_axi(11);
addrmap_w.VALIDFRAMECNT.data.data <= cdc_status_array_axi(43 downto 12);
addrmap_w.INVALIDFRAMECNT.data.data <= cdc_status_array_axi(75 downto 44);
addrmap_w.VALIDFRAMERATE.data.data <= cdc_status_array_axi(107 downto 76);
addrmap_w.INVALIDFRAMERATE.data.data <= cdc_status_array_axi(139 downto 108);
addrmap_w.FRAMESEQ.data.data <= cdc_status_array_axi(155 downto 140);
cdc_control_array_axi(0) <= addrmap_r.GT.RXRSTDATAPATH.data(0);
cdc_control_array_axi(1) <= addrmap_r.GT.RXRSTPLLDATAPATH.data(0);
cdc_control_array_axi(2) <= addrmap_r.GT.RXCOMMADETEN.data(0);
end block blk_desyrdl;
......@@ -234,8 +236,8 @@ begin
pps => pps,
gt_datarx => gt_datarx,
m_axis_m2s => m_axis_m2s,
m_axis_s2m => m_axis_s2m,
m_axis_m2s => m_axis_decoded_m2s,
m_axis_s2m => m_axis_decoded_s2m,
mc_time => mc_time,
soft_reset => addrmap_w.PROTOCOL.SOFTRESET.data(0),
......@@ -274,10 +276,10 @@ begin
qpll1refclk_in(0) => qpll_ref_clk,
-- Control
gtwiz_reset_rx_datapath_in => addrmap_r.GT.RXRSTDATAPATH.data,
gtwiz_reset_rx_pll_and_datapath_in => addrmap_r.GT.RXRSTPLLDATAPATH.data,
gtwiz_reset_rx_datapath_in(0) => cdc_control_array_bpm(0),
gtwiz_reset_rx_pll_and_datapath_in(0) => cdc_control_array_bpm(1),
rxbufreset_in => "0",
rxcommadeten_in => addrmap_r.GT.RXCOMMADETEN.data,
rxcommadeten_in(0) => cdc_control_array_bpm(2),
rx8b10ben_in => "1",
rxmcommaalignen_in => "1",
rxpcommaalignen_in => "1",
......@@ -323,4 +325,37 @@ begin
gtwiz_userclk_tx_usrclk_out => open,
gtwiz_userclk_tx_usrclk2_out => open
);
-------------------
-- PACKET FILTER --
-------------------
inst_filter:entity work.combpm_packet_filter
generic map(
G_W_ADDR_TABLE => C_W_ADDR_TABLE
)
port map(
axis_clk => usrclk,
axi_clk => s_axi_aclk,
axis_rst_n => sync_resetn,
-- AXIS SLAVE INTERFACE
s_axis_tdest => m_axis_decoded_m2s.tdest,
s_axis_tdata => m_axis_decoded_m2s.tdata,
s_axis_tvalid => m_axis_decoded_m2s.tvalid,
-- AXIS SLAVE INTERFACE
m_axis_tdest => m_axis_tdest,
m_axis_tdata => m_axis_tdata,
m_axis_tvalid => m_axis_tvalid,
-- Table configuration interface
pi_table_en => addrmap_r.table.en,
pi_table_we => addrmap_r.table.we,
pi_table_addr => addrmap_r.table.addr(C_W_ADDR_TABLE-1 downto 0),
pi_table_data => addrmap_r.table.data,
po_table_data => addrmap_w.table.data
);
end architecture struct;
rdl/combpm.rdl
View file @ 73ef0ccf
`include "combpm.vh" // Auto generated from FWK
addrmap combpm {
/* default values of defined variables */
`ifndef C_ID
`define C_ID 0x507E1710
`endif
desyrdl_generate_hdl = true;
addrmap combpm {
name="BPM protocol decoder controller";
desyrdl_interface = "AXI4L";
name="BPM protocol decoder controller";
reg {
desc="Module identifier.";
field {hw=w;sw=r;} data[32];
} ID;
reg {
desc="Module Identification Number";
default sw = r;
default hw = r;
field {} data[32] = `C_ID;
} ID @0x00;
reg {
desc="Module version.";
field {hw=w;sw=r;} data[32];
} VERSION;
} VERSION @0x04;
reg {
desc="SFP module status";
......@@ -109,4 +114,10 @@ addrmap combpm {
field {hw=w;sw=r;} data[16];
} FRAMESEQ;
external mem {
desc = "BPM filter table";
memwidth = 8;
mementries = 2**`C_W_ADDR_TABLE;
} TABLE @0x200;
};
tcl/generate_combpm_packet_filter_ip.tcl deleted 100644 → 0
View file @ 2236d275
# Address width, on logic side (8 bits data access)
set b_addr_w 14
# Address width on AXI MM side (32 bits access)
set a_addr_w [expr $b_addr_w-2]
set a_depth [expr 1<<$a_addr_w]
set b_depth [expr 1<<$b_addr_w]
set xcipath [create_ip -name axi_bram_ctrl -vendor xilinx.com -library ip -version 4.1 -module_name combpm_packet_filter_axi_bram_ctrl]
set_property -dict [list \
CONFIG.PROTOCOL {AXI4} \
CONFIG.SUPPORTS_NARROW_BURST {0} \
CONFIG.SINGLE_PORT_BRAM {1} \
CONFIG.USE_ECC {0} \
CONFIG.BMG_INSTANCE {EXTERNAL} \
CONFIG.MEM_DEPTH $a_depth \
CONFIG.CLKIF.FREQ_HZ 250000000 \
CONFIG.DATA_WIDTH 32 \
] [get_ips combpm_packet_filter_axi_bram_ctrl]
set_property GENERATE_SYNTH_CHECKPOINT 0 [get_files $xcipath]
set xcipath [create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name combpm_packet_filter_blk_mem]
set_property -dict [list \
CONFIG.Memory_Type {True_Dual_Port_RAM} \
CONFIG.Use_Byte_Write_Enable {true} \
CONFIG.Byte_Size {8} \
CONFIG.Write_Width_A {32} \
CONFIG.Write_Depth_A $a_depth \
CONFIG.Read_Width_A {32} \
CONFIG.Operating_Mode_A {WRITE_FIRST} \
CONFIG.Write_Width_B {8} \
CONFIG.Read_Width_B {8} \
CONFIG.Operating_Mode_B {WRITE_FIRST} \
CONFIG.Enable_B {Use_ENB_Pin} \
CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \
CONFIG.Register_PortA_Output_of_Memory_Core {false} \
CONFIG.Register_PortB_Output_of_Memory_Primitives {false} \
CONFIG.Port_B_Clock {250} \
CONFIG.Port_B_Write_Rate {0} \
CONFIG.Port_B_Enable_Rate {100} \
] [get_ips combpm_packet_filter_blk_mem]
set_property GENERATE_SYNTH_CHECKPOINT 0 [get_files $xcipath]
tcl/main.tcl
View file @ 73ef0ccf
......@@ -4,11 +4,13 @@
# ==============================================================================
proc init {} {
variable Config
# Configuration from package
parseVhdlConfigFile Config "../hdl/pkg_combpm.vhd"
# TODO add quad to configuration
# Configuration
# TODO Follow FWK
# variable quad_name
# set quad_name X0Y4
}
# ==============================================================================
......@@ -19,6 +21,7 @@ proc setSources {} {
genModVerFile VHDL ../hdl/pkg_combpm_version.vhd
lappend Vhdl ../hdl/pkg_combpm_version.vhd
lappend Vhdl ../hdl/pkg_combpm.vhd
lappend Vhdl ../hdl/combpm_protocol_electron.vhd
lappend Vhdl ../hdl/top_combpm_electron.vhd
lappend Vhdl ../hdl/pkg_bpmpacket_stream.vhd
......@@ -46,8 +49,6 @@ proc doOnCreate {} {
set_property target_language VHDL [current_project]
source combpm_gtwizard.tcl
source generate_combpm_packet_filter_ip.tcl
variable Vhdl
addSources Vhdl
}
......

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