* Remove pkg_bpmpacket_stream
* now be explicit on fields inside tdata

* Packet filter now uses DESYLIB true dual port RAM.
* Add a packet filter before the module output.
* Add packet filter as external memory in rdl.

* One clock domain for AXI-MM
* One for COM BPM logic
* Xilinx CDC in between (control and status registers).
* Also move component declaration in a package