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Commit d4c7e5a3 authored by BRONES Romain's avatar BRONES Romain
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feat:Change and incorporate packet filter 

* Packet filter now uses DESYLIB true dual port RAM.
* Add a packet filter before the module output.
* Add packet filter as external memory in rdl.
parent eaabf330
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hdl/combpm_packet_filter.vhd
+ 46
− 186
View file @ d4c7e5a3
......@@ -4,15 +4,17 @@ use ieee.numeric_std.all;
use work.pkg_bpmpacket_stream.all;
library desy;
use desy.ram_tdp;
entity combpm_packet_filter is
generic(
G_B_ADDR_W : natural := 14
G_W_ADDR_TABLE : natural
);
port(
axis_clk : in std_logic;
axi_clk : in std_logic;
axis_rst_n : in std_logic;
axi_rst_n : in std_logic;
-- AXIS SLAVE INTERFACE
s_axis_tdest : in std_logic_vector(C_TDEST_W-1 downto 0);
......@@ -21,128 +23,31 @@ entity combpm_packet_filter is
s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic;
-- AXIS SLAVE INTERFACE
-- AXIS MASTER INTERFACE
m_axis_tdest : out std_logic_vector(C_TDEST_W-1 downto 0);
m_axis_tdata : out std_logic_vector(C_TDATA_W-1 downto 0);
m_axis_tlast : out std_logic;
m_axis_tvalid : out std_logic;
-- AXI bus interface
s_axi_awaddr : IN STD_LOGIC_VECTOR(G_B_ADDR_W-1 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(G_B_ADDR_W-1 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
-- Table configuration interface
pi_table_en : in std_logic;
pi_table_we : in std_logic;
pi_table_addr : in std_logic_vector(G_W_ADDR_TABLE-1 downto 0);
pi_table_data : in std_logic_vector(7 downto 0);
po_table_data : out std_logic_vector(7 downto 0)
);
end combpm_packet_filter;
architecture rtl of combpm_packet_filter is
---------------------------
-- COMPONENT DECLARATION --
---------------------------
COMPONENT combpm_packet_filter_axi_bram_ctrl
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(G_B_ADDR_W-1 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(G_B_ADDR_W-1 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(G_B_ADDR_W-1 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT combpm_packet_filter_blk_mem
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(G_B_ADDR_W-3 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(G_B_ADDR_W-1 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
-- SIGNAL DECLARATION --
------------------------
signal in_packet : t_bpmpacket;
signal out_packet : t_bpmpacket;
signal bram_clk_a : STD_LOGIC;
signal bram_en_a : STD_LOGIC;
signal bram_we_a : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal bram_addr_a : STD_LOGIC_VECTOR(G_B_ADDR_W-3 DOWNTO 0);
signal bram_wrdata_a : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal bram_rddata_a : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal table_data : std_logic_vector(7 downto 0);
signal tvalid_r : std_logic_vector(1 downto 0);
......@@ -186,73 +91,28 @@ begin
m_axis_tlast <= '1'; -- Packet is one tdata only
m_axis_tvalid <= tvalid_r(tvalid_r'left) and table_data(7);
---------------------
-- BRAM CONTROLLER --
---------------------
inst_bram_ctrl : combpm_packet_filter_axi_bram_ctrl
port map (
s_axi_aclk => axi_clk,
s_axi_aresetn => axi_rst_n,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
bram_rst_a => open,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a(1 downto 0) => open,
bram_addr_a(G_B_ADDR_W-1 downto 2) => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a
);
-------------------
-- BRAM INSTANCE --
-------------------
inst_bram : combpm_packet_filter_blk_mem
------------------
-- FILTER TABLE --
------------------
-- Port A is read write from AXI controller, Port B is read only from logic
inst_phase_table: entity desy.ram_tdp
generic map(
G_ADDR => G_W_ADDR_TABLE,
G_DATA => 8
)
port map(
clka => bram_clk_a,
ena => bram_en_a,
wea => bram_we_a,
addra => bram_addr_a,
dina => bram_wrdata_a,
douta => bram_rddata_a,
clkb => axis_clk,
enb => '1',
web => "0",
addrb => in_packet.bpm_id(G_B_ADDR_W-1 downto 0),
dinb => (others => '0'),
doutb => table_data
pi_clk_a => axi_clk,
pi_en_a => pi_table_en,
pi_we_a => pi_table_we,
pi_addr_a => pi_table_addr,
pi_data_a => pi_table_data,
po_data_a => po_table_data,
pi_clk_b => axis_clk,
pi_en_b => '1',
pi_we_b => '0',
pi_addr_b => in_packet.bpm_id(G_W_ADDR_TABLE-1 downto 0),
pi_data_b => (others => '0'),
po_data_b => table_data
);
end architecture rtl;
hdl/pkg_combpm.vhd
+ 3
− 0
View file @ d4c7e5a3
......@@ -7,6 +7,9 @@ use ieee.numeric_std.all;
package pkg_combpm is
constant C_W_ADDR_TABLE : natural := 8;
-------------------------
-- GT WIZARD COMPONENT --
-------------------------
......
hdl/top_combpm_electron.vhd
+ 44
− 4
View file @ d4c7e5a3
......@@ -48,8 +48,10 @@ entity top_combpm_electron is
-- AXIS interface
m_axis_aclk : out std_logic;
m_axis_m2s : out t_bpmpacket_axis_m2s;
m_axis_s2m : in t_bpmpacket_axis_s2m; -- warning: TREADY is ignored !
m_axis_tdata : out std_logic_vector(C_TDATA_W-1 downto 0);
m_axis_tdest : out std_logic_vector(C_TDEST_W-1 downto 0);
m_axis_tlast : out std_logic;
m_axis_tready : in std_logic;
-- AXI bus interface
s_axi_aclk : in std_logic;
......@@ -93,6 +95,8 @@ architecture struct of top_combpm_electron is
signal cdc_control_array_axi : std_logic_vector(2 downto 0); -- CDC, clock axi side
signal cdc_control_array_bpm : std_logic_vector(2 downto 0); -- CDC, clock bpm side
signal m_axis_decoded_m2s : t_bpmpacket_axis_m2s;
signal m_axis_decoded_s2m : t_bpmpacket_axis_s2m; -- warning: TREADY is ignored !
begin
......@@ -234,8 +238,8 @@ begin
pps => pps,
gt_datarx => gt_datarx,
m_axis_m2s => m_axis_m2s,
m_axis_s2m => m_axis_s2m,
m_axis_m2s => m_axis_decoded_m2s,
m_axis_s2m => m_axis_decoded_s2m,
mc_time => mc_time,
soft_reset => addrmap_w.PROTOCOL.SOFTRESET.data(0),
......@@ -323,4 +327,40 @@ begin
gtwiz_userclk_tx_usrclk_out => open,
gtwiz_userclk_tx_usrclk2_out => open
);
-------------------
-- PACKET FILTER --
-------------------
inst_filter:entity work.combpm_packet_filter
generic map(
G_W_ADDR_TABLE => C_W_ADDR_TABLE
)
port map(
axis_clk => usrclk,
axi_clk => s_axi_aclk,
axis_rst_n => sync_resetn,
-- AXIS SLAVE INTERFACE
s_axis_tdest => m_axis_decoded_m2s.tdest,
s_axis_tdata => m_axis_decoded_m2s.tdata,
s_axis_tlast => m_axis_decoded_m2s.tlast,
s_axis_tvalid => m_axis_decoded_m2s.tvalid,
s_axis_tready => m_axis_decoded_s2m.tready,
-- AXIS SLAVE INTERFACE
m_axis_tdest => m_axis_tdest,
m_axis_tdata => m_axis_tdata,
m_axis_tlast => m_axis_tlast,
m_axis_tvalid => m_axis_tvalid,
-- Table configuration interface
pi_table_en => addrmap_r.table.en,
pi_table_we => addrmap_r.table.we,
pi_table_addr => addrmap_r.table.addr(C_W_ADDR_TABLE-1 downto 0),
pi_table_data => addrmap_r.table.data,
po_table_data => addrmap_w.table.data
);
end architecture struct;
rdl/combpm.rdl
+ 6
− 0
View file @ d4c7e5a3
......@@ -109,4 +109,10 @@ addrmap combpm {
field {hw=w;sw=r;} data[16];
} FRAMESEQ;
external mem {
desc = "BPM filter table";
memwidth = 8;
mementries = 2**`C_W_ADDR_TABLE;
} TABLE;
};
tcl/generate_combpm_packet_filter_ip.tcl deleted 100644 → 0
+ 0
− 49
View file @ eaabf330
# Address width, on logic side (8 bits data access)
set b_addr_w 14
# Address width on AXI MM side (32 bits access)
set a_addr_w [expr $b_addr_w-2]
set a_depth [expr 1<<$a_addr_w]
set b_depth [expr 1<<$b_addr_w]
set xcipath [create_ip -name axi_bram_ctrl -vendor xilinx.com -library ip -version 4.1 -module_name combpm_packet_filter_axi_bram_ctrl]
set_property -dict [list \
CONFIG.PROTOCOL {AXI4} \
CONFIG.SUPPORTS_NARROW_BURST {0} \
CONFIG.SINGLE_PORT_BRAM {1} \
CONFIG.USE_ECC {0} \
CONFIG.BMG_INSTANCE {EXTERNAL} \
CONFIG.MEM_DEPTH $a_depth \
CONFIG.CLKIF.FREQ_HZ 250000000 \
CONFIG.DATA_WIDTH 32 \
] [get_ips combpm_packet_filter_axi_bram_ctrl]
set_property GENERATE_SYNTH_CHECKPOINT 0 [get_files $xcipath]
set xcipath [create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name combpm_packet_filter_blk_mem]
set_property -dict [list \
CONFIG.Memory_Type {True_Dual_Port_RAM} \
CONFIG.Use_Byte_Write_Enable {true} \
CONFIG.Byte_Size {8} \
CONFIG.Write_Width_A {32} \
CONFIG.Write_Depth_A $a_depth \
CONFIG.Read_Width_A {32} \
CONFIG.Operating_Mode_A {WRITE_FIRST} \
CONFIG.Write_Width_B {8} \
CONFIG.Read_Width_B {8} \
CONFIG.Operating_Mode_B {WRITE_FIRST} \
CONFIG.Enable_B {Use_ENB_Pin} \
CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \
CONFIG.Register_PortA_Output_of_Memory_Core {false} \
CONFIG.Register_PortB_Output_of_Memory_Primitives {false} \
CONFIG.Port_B_Clock {250} \
CONFIG.Port_B_Write_Rate {0} \
CONFIG.Port_B_Enable_Rate {100} \
] [get_ips combpm_packet_filter_blk_mem]
set_property GENERATE_SYNTH_CHECKPOINT 0 [get_files $xcipath]
tcl/main.tcl
+ 6
− 6
View file @ d4c7e5a3
......@@ -4,11 +4,13 @@
# ==============================================================================
proc init {} {
variable Config
# Configuration from package
parseVhdlConfigFile Config "../hdl/pkg_combpm.vhd"
# TODO add quad to configuration
# Configuration
# TODO Follow FWK
# variable quad_name
# set quad_name X0Y4
}
# ==============================================================================
......@@ -47,8 +49,6 @@ proc doOnCreate {} {
set_property target_language VHDL [current_project]
source combpm_gtwizard.tcl
source generate_combpm_packet_filter_ip.tcl
variable Vhdl
addSources Vhdl
}
......
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