Add False path

*  Still need to confirm

con/combpm_timing.xdc

+
+set_false_path -from [get_clocks -of_objects [get_pins -hierarchical -regexp -filter { NAME =~  ".*inst_filter/inst_filter_table/addr_a.*" && IS_CLOCK == "TRUE" }]] -through [get_nets -hierarchical -regexp -filter { NAME =~  ".*inst_filter/table_data.*" }]

hdl/combpm_packet_filter.vhd

@@ -92,7 +92,7 @@ begin
     -- FILTER TABLE --
     ------------------
     -- Port A is read write from AXI controller, Port B is read only from logic
-    inst_phase_table: entity desy.ram_tdp
+    inst_filter_table: entity desy.ram_tdp
     generic map(
         G_ADDR  => G_W_ADDR_TABLE,
         G_DATA  => 8

tcl/main.tcl

@@ -15,16 +15,17 @@ proc init {} {
 
 # ==============================================================================
 proc setSources {} {
-  variable Vhdl
+  variable Sources
 
   # Generate VHDL package with modversion
   genModVerFile VHDL ../hdl/pkg_combpm_version.vhd
 
-  lappend Vhdl {"../hdl/pkg_combpm_version.vhd" "VHDL 2008"}
-  lappend Vhdl {"../hdl/pkg_combpm.vhd" "VHDL 2008"}
-  lappend Vhdl {"../hdl/combpm_protocol_electron.vhd" "VHDL 2008"}
-  lappend Vhdl {"../hdl/top_combpm_electron.vhd" "VHDL 2008"}
-  lappend Vhdl {"../hdl/combpm_packet_filter.vhd" "VHDL 2008"}
+  lappend Sources {"../hdl/pkg_combpm_version.vhd" "VHDL 2008"}
+  lappend Sources {"../hdl/pkg_combpm.vhd" "VHDL 2008"}
+  lappend Sources {"../hdl/combpm_protocol_electron.vhd" "VHDL 2008"}
+  lappend Sources {"../hdl/top_combpm_electron.vhd" "VHDL 2008"}
+  lappend Sources {"../hdl/combpm_packet_filter.vhd" "VHDL 2008"}
+  lappend Sources {"../con/combpm_timing.xdc" "XDC"}
 
 }
 
@@ -48,8 +49,8 @@ proc doOnCreate {} {
   set_property target_language VHDL [current_project]
   source combpm_gtwizard.tcl
 
-  variable Vhdl
-  addSources Vhdl
+  variable Sources
+  addSources Sources
 }
 
 # ==============================================================================