Add debug ports, add reset PLL and datapath

* Add debug ports of transceiver data and status before the protocole
  decoder.
* Add a reset bit for PLL and datapath in AXI-MM interface.

hdl/top_combpm_electron.vhd

@@ -23,6 +23,10 @@ entity top_combpm_electron is
         qpll_reset           : out std_logic;   -- QPLL reset
         qpll_lock            : in std_logic;    -- QPLL is locked
 
+        -- Debug output
+        debug_datarx         : out std_logic_vector(15 downto 0);
+        debug_status         : out std_logic_vector(3 downto 0);
+
         -- SFP interfaces
         sfp_txp              : out std_logic;
         sfp_txn              : out std_logic;
@@ -172,6 +176,7 @@ architecture struct of top_combpm_electron is
     signal gt_rxcommadet      : std_logic;
     signal gt_rxcommadeten    : std_logic;
     signal gt_rxresetdatapath : std_logic;
+    signal gt_rxresetplldatapath : std_logic;
 
 begin
 
@@ -193,6 +198,20 @@ begin
     rst <= not rst_n;
     sync_reset <= not sync_resetn;
 
+    -- Debug
+    debug_datarx        <= gt_datarx;
+    debug_status(0)     <= gt_rxcommadet;
+    debug_status(1)     <= gt_rxcdrlock;
+    debug_status(2)     <= gt_rxbyterealign;
+    debug_status(3)     <= gt_rxbyteisaligned;
+
+    -- Output clock
+    clk <= usrclk;
+
+    -- SFP direct connexion
+    sfp_tx_disable  <= '1';
+
+
     ----------------------
     -- AXI-MM INTERFACE --
     ----------------------
@@ -213,6 +232,7 @@ begin
         gt_rxcommadet_i       => gt_rxcommadet,
         gt_rxcommadeten_o     => gt_rxcommadeten,
         gt_rxrstdatapath_o    => gt_rxresetdatapath,
+        gt_rxrstplldatapath_o => gt_rxresetplldatapath,
         protocol_framecnt_i   => frame_counter,
         protocol_frameerror_i => frame_error,
         protocol_softreset_o  => soft_reset,
@@ -293,6 +313,7 @@ begin
 
         -- Control
         gtwiz_reset_rx_datapath_in(0)         => gt_rxresetdatapath,
+        gtwiz_reset_rx_pll_and_datapath_in(0) => gt_rxresetplldatapath,
         rxbufreset_in                         => "0",
         rxcommadeten_in(0)                    => gt_rxcommadeten,
         rx8b10ben_in                          => "1",
@@ -301,7 +322,6 @@ begin
         tx8b10ben_in                          => "1",
         gtwiz_reset_tx_pll_and_datapath_in    => "0",
         gtwiz_reset_tx_datapath_in            => "0",
-        gtwiz_reset_rx_pll_and_datapath_in    => "0",
 
         -- Status
         gtwiz_userclk_tx_active_out           => open,
@@ -341,10 +361,4 @@ begin
         gtwiz_userclk_tx_usrclk_out           => open,
         gtwiz_userclk_tx_usrclk2_out          => open
     );
-
-    clk <= usrclk;
-
-    -- SFP direct connexion
-    sfp_tx_disable  <= '1';
-
 end architecture struct;

rdl/combpm_protocol_electron_ctrl.rdl

@@ -85,6 +85,12 @@ addrmap combpm_ctrl {
             sw=rw;
         } RXRSTDATAPATH = 1;
 
+        field {
+            desc="Reset RX PLL and datapath";
+            hw=r;
+            sw=rw;
+        } RXRSTPLLDATAPATH = 1;
+
     } GT;
 
     reg {